Agilent HDMP-1687
Four Channel SerDes Circuit
for Gigabit Ethernet and
Fibre Channel
Data Sheet
Features
• Four ANSI x3.230- 1994 Fibre Chan-
nel (FC-O) or IEEE 802.3z Gigabit
Ethernet compatible SerDes in
a single package
• Supports serial data rates of 1062.5
MBd (Fibre Channel) & 1250 MBd
(Gigabit Ethernet)
• Based on X3T11 Fibre Channel
”10 bit specification“
• Uses reference clock (RFCT) for Tx
data latching
• Half or full speed Rx clocks
• 5-Volt tolerant TTL I/Os
• Low power consumption
• 208 ball, 23 mm TBGA package
• Single +3.3 V power supply
• 1.5 kV ESD protection on all pins
• Equalizers on inputs
• Copper drive capability
• Buffered line logic outputs
Applications
• 1250 MBd Gigabit Ethernet high
density ports
• 1062.5 MBd Fibre Channel interface
• Mass storage system I/O channel
• Work station/server I/O channel
• FC interface for disk drives and
arrays
• Serial backplanes
• Clusters
per the 8B/10B encoding scheme,
with special reserve characters for
link management purposes. Other
encoding schemes will also work
as long as they provide dc balance
and sufficient transition density.
In order to accomplish this task,
the SERDES circuitry incorporates
the following:
Functional Description
The HDMP-1687 is a four channel
SERDES device. HDMP-1687 is in a
208-ball TBGA package with four
1.0625/1.25 Gbps serial I/O. This
integrated circuit provides a low-
cost, low-power, small-form-factor
physical-layer solution for multi-link
Gigabit Ethernet/Fibre Channel
interfaces. This IC may be used to
directly drive copper cables, or it
may be used to interface with opti-
cal transceivers. Each IC contains
transmit and receive channel cir-
cuitry for all four channels.
The transmitter section accepts
10-bit-wide parallel TTL data on
each channel and serializes it into
a high-speed serial stream. The
parallel data is expected to be
8B/10B encoded (or equivalent).
Four banks of parallel data are
latched into the input registers of
the transmitter sections on the ris-
ing edge of RFCT.
Receive data are latched out with
separate clock pins for each chan-
nel. These pins may be single
106.25/125 MHz TTL clock outputs
RC [0:3] [1] or dual 53.125/62.5
MHz TTL pairs RC [0:3] [0:1] to
serve legacy applications where
single SerDes devices were used
before. The receive clock mode
select (RCM0) pin is used to de-
fine the designer’s choice.
RCM0 Receive Clock Mode
0
half speed dual clocks
1
full speed single clocks
The SYNC pin enables bytesync
detection on all four channels.
When a comma character is
detected on any channel, its corre-
sponding SYN [0:3] pin goes high.
A single LOOP pin is provided for
all channels to enable the local
loopback function.
HDMP-1687 Block Diagram
The following is a description of
the blocks in each channel. Ex-
cept for the transmit PLL section,
circuits for the channels are inde-
pendent. Figure 1 shows how this
IC may be connected to a protocol
device that controls four channels.
Each channel of the four channel
SERDES (Figure 2) was designed
to transmit and receive 10-bit-
wide characters over dedicated
differential high-speed lines. The
parallel data applied to the trans-
mitter is expected to be encoded
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
