10-2
10-3
10-4
stripline transmission lines. This
will help to minimize the parasitic
inductance and capacitance
board is best for distribution of
, returning ground currents,
forming transmission lines and
LINEAR EXTRAPOLATION OF
10-4 THROUGH 10-7 DATA
V
CC
BASED ON
ACTUAL DATA
effects. Proper termination of the shielding, Also, it is important to
10-5
10-6
10-7
differential data signals will
prevent reflections and ringing
which would compromise the
signal fidelity and generate
unwanted electrical noise. Locate supply filtering of V for this
termination at the received signal transceiver is accomplished by
end of the transmission line. The
length of these lines should be
kept short and of equal length.
For the high speed signal lines,
differential signals should be
used, not single-ended signals,
and these differential signals
need to be loaded symmetrically
to prevent unbalanced currents
from flowing which will cause
distortion in the signal.
suppress noise from influencing
the fiber-optic transceiver
performance, especially the
receiver circuit. Proper power
10-8
10-9
10-10
10-11
10-12
10-13
10-14
10-15
CC
using the recommended, separate
filter circuits shown in Figure 3
for the transmitter and receiver
sections. These filter circuits
-5 -4 -3 -2 -1
0
1
2
3
Figure 2. Relative Input Optical Power
- dBm. Avg.
suppress V noise over a broad
CC
Recommended Circuit Schematic
In order to ensure proper
functionality of the HFCT-5805 a
recommended circuit is provided
in Figure 3. When designing the
circuit interface, there are a few
fundamental guidelines to follow.
For example, in the Recommended
Circuit Schematic figure the
frequency range, this prevents
receiver sensitivity degradation
due to V noise. It is
CC
recommended that surface-mount
components be used. Use
tantalum capacitors for the 10 µF
capacitors and monolithic,
ceramic bypass capacitors for the
0.1 µF capacitors. Also, it is
recommended that a surface-
mount coil inductor of 3.3 µH be
Maintain a solid, low inductance
ground plane for returning signal
currents to the power supply.
Multilayer plane printed circuit
differential data lines should be
treated as 50 ohm Microstrip or
NO INTERNAL
CONNECTION
NO INTERNAL
CONNECTION
TOP VIEW
Rx
VEER
1
Rx
Tx
Tx
VEET
9
VCCR VCCT
5
RD
2
SD
4
TD
8
RD
3
TD
7
6
C2 C8
L1 L2
C1 C7
NOTES:
VCC
THE SPLIT-LOAD TERMINATIONS FOR LVPECL
SIGNALS NEED TO BE LOCATED AT THE INPUT OF
DEVICES RECEIVING THOSE LVPECL SIGNALS.
RECOMMEND 4-LAYER PRINTED CIRCUIT BOARD
WITH 50 W MICROSTRIP SIGNAL PATHS BE USED.
R1 = R4 = R6 = R8 = R10 = 82 W
R2 = R3 = R5 = R7 = R9 = 130 W
C1 = C2 = 10 µF
C3 = C4 = C7 = C8 = 100 nF
R2 R3
VCC
C3
C4
TERMINATE
AT PHY
R5 R7
C6
C5
R1
Vcc FILTER
AT Vcc PINS
TRANSCEIVER
R4
DEVICE
INPUTS
TERMINATION
AT
TRANSCEIVER
INPUTS
R6
R8
R10 R9
C5 = C6 = 0.1 µF
TD
L1 = L2 = 3.3 µH COIL OR FERRITE INDUCTOR.
VCC
TD
RD RD
SD
Figure 3. Recommended Circuit Schematic
3
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
