MGA-71543 Electrical Specifications
T
c
= +25°C, Z
o
= 50Ω, I
d
= 10 mA, V
d
= 3V, unless noted
Symbol
Vref test
NF test
Gain test
IIP3 test
Gain, Bypass
Ig test
NFmin
[3]
Parameter and Test Condition
Vds = 2.4 V
f = 2.01 GHz
f = 2.01 GHz
f = 2.01 GHz
V
d
= 3.0 V (= Vds - Vref)
V
d
= 3.0 V (= Vds - Vref)
V
d
= 3.0 V (= Vds - Vref)
I
d
= 10 mA
I
d
= 10 mA
I
d
= 10 mA
I
d
= 10 mA
I
d
= 0 mA
I
d
= 0 mA
f = 0.9 GHz
f = 1.5 GHz
f = 1.9 GHz
f = 2.1 GHz
f = 2.5 GHz
f = 6.0 GHz
f = 0.9 GHz
f = 1.5 GHz
f = 1.9 GHz
f = 2.1 GHz
f = 2.5 GHz
f = 6.0 GHz
I
d
= 0 mA
I
d
= 3 mA
I
d
= 6 mA
I
d
= 10 mA
I
d
= 20 mA
I
d
= 40 mA
I
d
= 0 mA
I
d
= 3 mA
I
d
= 6 mA
I
d
= 10 mA
I
d
= 20 mA
I
d
= 40 mA
Intrinsic
Eval Circuit
f = 2.01 GHz
f = 2.01 GHz
f = 2.01 GHz
Units
V
dB
dB
dBm
dB
µA
dB
Min.
-0.86
Typ.
-0.65
1.1
Max.
-0.43
1.45
17.4
σ
[1]
0.041
0.02
0.24
0.96
0.12
1.5
14.4
1
-6.4
15.9
4.3
-5.6
2.0
0.7
0.7
0.8
0.8
0.8
1.1
17.1
16.4
15.8
15.4
14.9
10.0
+10
-5.1
+3.0
+7.4
+13.1
+15.5
+35
-2.6
+1.6
+4.3
+7.4
+8.7
10
100
6.0
10.9
-22.5
f = 2.01 GHz
Vds = 0 V, Vref = -3V
Bypass Mode
[6]
Bypass Mode Vds = 0 V, Vref = -3 V
[6]
Minimum Noise Figure
As measured in Figure 5 Test Circuit
(Γopt computed from s-parameter and
noise parameter performance as measured
in a 50Ω impedance fixture)
Associated Gain at Nfo
As measured in Figure 5 Test Circuit
(Gopt computed from s-parameter and
noise parameter performance as measured
in a 50Ω impedance fixture)
Output Power at 1 dB Gain Compression
As measured in Evaluation Test Circuit with
source resistor biasing
[4,5]
Frequency = 2.01 GHz
Gass
[3]
dB
P1dB
dBm
IIP3
Input Third Order Intercept Point
As measured in Figure 4 Test Circuit
[5]
Frequencies = 2.01 GHz, 2.02 GHz
dBm
Switch
Bypass Switch Rise/Fall Time
(10% - 90%)
As measured in Evaluation Test Circuit
Input Return Loss as measured in Fig. 4
Output Return Loss as measured in Fig. 4
Isolation |s12|
2
as measured in Fig. 5
nS
dB
dB
dB
RLin
RLout
ISOL
0.31
0.65
Notes:
1. Standard Deviation and Typical Data based at least 450 part sample size from 9 wafers. Future wafers allocated to this product may have nominal
values anywhere within the upper and lower spec limits.
2. Measurements made on a fixed tuned production test circuit (Figure 4) that represents a trade-off between optimal noise match, maximum gain
match, and a realizable match based on production test board requirements at 10 mA bias current. Excess circuit losses have been de-embedded
from actual measurements. Vd=Vds-Vref where Vds is adjusted to maintain a constant Vd bias equivalent to a single supply 3V bias application.
Consult Applications Note for circuit biasing options.
3. Minimum Noise Figure and Associated Gain data computed from s-parameter and noise parameter data measured in a 50Ω system using ATN NP5
test system. Data based on 10 typical parts from 9 wafers. Associated Gain is the gain when the product input is matched for minimum Noise Figure.
4. P1dB measurements were performed in the evaluation circuit with source resistance biasing. As P1dB is approached, the drain current is
maintained near the quiescent value by the feedback effect of the source resistor in the evaluation circuit. Consult Applications Note for circuit
biasing options.
5. Measurements made on a fixed tuned production test circuit that represents a trade-off between optimal noise match, maximum gain match, and a
realizable match based on production test board requirements at 10 mA bias current. Performance may be optimized for different bias conditions
and applications. Consult Applications Note.
6. The Bypass Mode test conditions are required only for the production test circuit (Figure 4) using the gate bias method. In the preferred source
resistor bias configuration, the Bypass Mode is engaged by presenting a DC open circuit instead of the bias resistor on Pin 4.
3
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