14
OUTPUT
& V
50
40
30
20
current in the bypass state is
nominally 2 µA.
INPUT
d
3
2
4
1
Biasing
Biasing the MGA-72543 is similar
to biasing a discrete GaAs FET.
Passive biasing of the MGA-72543
may be accomplished by either of
two conventional methods, either
by biasing the gate or by using a
source resistor.
R
bias
Figure 4. Source Resistor Bias.
10
0
A simple method recommended
for DC grounding the input
terminal is to merely add a
resistor from Pin 3 to ground, as
shown in Figure 4. The value of
the shunt R can be comparatively
high since the only voltage drop
across it is due to minute leakage
currents that in the µA range. A
value of 1 KΩ would adequately
DC ground the input while
loading the RF signal by only
0.2 dB loss.
-0.80 -0.70 -0.60 -0.50 -0.40 -0.30 -0.20
V
(V)
ref
• Gate Bias
Figure 3. Device Current vs. V
.
ref
Using this method, Pins 1 and 4 of
the amplifier are DC grounded
and a negative bias voltage is
applied to Pin 3 as shown in
Figure 2. This method has the
advantage of not only DC, but
also RF grounding both of the
ground pins of the MGA-72543.
Direct RF grounding of the
device’s ground pins results in
slightly improved performance
while decreasing potential
instabilities, especially at higher
frequencies. The disadvantage is
that a negative supply voltage is
required.
The device current may also be
estimated from the following
equation:
V
= 0.11 I – 0.96
√
ref
d
where I is in mA and V is in
volts.
d
ref
The gate bias method would not
normally be used unless a nega-
tive supply voltage was readily
available. For reference, this is
the method used in the character-
ization test circuits shown in
Figures 1 and 2 of the MGA-72543
data sheet.
A plot of typical I vs. R
shown in Figure 5.
is
bias
d
60
50
40
30
20
• Source Resistor Bias
OUTPUT
& V
INPUT
d
The source resistor method is the
simplest way of biasing the
MGA-72543 using a single,
positive supply voltage. This
method, shown in Figure 4,
places the RF Input (Pin 3) at DC
ground and requires both of the
device grounds (Pins 1 and 4) to
be RF bypassed. Device current,
3
2
1
4
10
0
0
20 40
60
80 100 120 140
V
ref
R
(Ω)
bias
Figure 2. Gate Bias Method.
Figure 5. Device Current vs. R
.
bias
DC access to the input terminal
for applying the gate bias voltage
can be made through either a
RFC or high impedance transmis-
sion line as indicated in Figure 2.
I , is determined by the value of
the source resistance, R
d
The approximate value of the
external resistor, R , may also
,
bias
bias
between either Pin 1 or Pin 4 of
the MGA-72543 and DC ground.
Note: Pins 1 and 4 are connected
internally in the RFIC. Maximum
device current (approximately
be calculated from:
964
R
=
(1 – 0.112 I )
d
√
bias
I
d
The device current, I , is deter-
d
mined by the voltage at V
ref
where R
is in ohms and I is
d
the desired device current in mA.
65 mA) occurs for R
= 0.
bias
bias
(Pin 3) with respect to ground. A
plot of typical I vs. V is shown
d
ref
in Figure 3. Maximum device
current (approximately 65 mA)
occurs at V = 0.
ref
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
