8
40
30
20
L2 (nH)
10
9
8
7
6
5
4
3
2
The starting place is to design a
circuit that matches the small
signal
Γ
ml
(the reflection coeffi-
cient of the load impedance
required to conjugately match the
output of the MGA-83563) to
50 ohms. The small signal
S-parameter data for designing
the output circuit is taken from
Table 1, using the data corre-
sponding to be nearest value of
interstage inductor that was
chosen in step one.
A RF CAD program such as
Agilent’s
Touchstone
can be used
to easily calculate
Γ
ml
.
Touch-
stone
will interpolate the Table 1
S-parameter data for the particu-
lar design frequency of interest.
As the MGA-83563 is driven into
saturation, the output impedance
will generally become lower.
Choose a circuit topology that
will match
Γ
ml
as well as the
range of impedances on the low
side of
Γ
ml
. Beginning with this
small signal output match, tune
the circuit under large signal
conditions for maximum
saturated output power and best
efficiency.
It should be noted that both the
saturated output power (P
sat
) and
power-added efficiency (PAE) for
each MGA-83563 is 100% RF
tested at 2.4 GHz in a production
test fixture that simulates an
actual amplifier application. This
method of testing not only
guarantees minimum
performance standards, but also
ensures repeatable RF
performance in the user’s
production circuits.
1
0.9
0.8
0.7
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
Figure 19. Values for Interstage Inductor L2.
supply side of the RFC is capaci-
tively bypassed. A DC blocking
capacitor is used at the output to
isolate the supply voltage from
the succeeding stage.
In order to prevent loss of output
power, the value of the RFC is
chosen such that its reactance is
several hundred ohms at the
frequency band of operation. At
higher frequencies, it may be
practical to use a length of high
impedance transmission line
(preferably
λ/4)
in place of the
RFC.
The value of the DC blocking and
RF bypass capacitors are chosen
to provide a small reactance
(typically < 1Ω) at the lowest
operating frequency.
Since both stages of the RFIC are
biased from the same voltage
source, particular care should be
taken to ensure that the supply
line between the two is well
bypassed to prevent inadvertent
feedback from the RF output to
the drain of the first stage.
Otherwise, the circuit could
become unstable.
The RF Input (Pin 3) connection
to the MGA-83563 is at DC ground
potential. The use of a DC
blocking capacitor at the input of
the MGA-83563 is not required
unless a circuit that has a DC
voltage present at its output
precedes the RFIC. Although at
ground potential, the input to the
MGA-83563 should not be used as
a current sink.
Step 3 —
Output Impedance Match
The most interesting aspect of
using the MGA-83563 is arriving
at an optimum, large signal
impedance match at the output. A
simple but effective approach is
to begin with a circuit that
provides a small signal imped-
ance match, then empirically
adjust the tuning for optimum
large signal performance.
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
