AIC3842
n
BLOCK DIAGRAM
VCC
7
ZD
34V
UVLO
S/R
5V
REF
Internal Bias
2.50V
4
RT/CT
OSC
Error Amp.
2
VFB
1
COMP
3
ISENSE
D1
D2
R2
Z1
1V
PWM
Latch
Q2
VREF
Good
Logic
8
V
REF
5V/50mA
5
GND
Q1
6
OUTPUT
S
R
Current
Sense
comparator
n
PIN DESCRIPTIONS
PIN 1: COMP
- This pin is the error amplifier
output and is made available for
loop compensation.
PIN 2: VFB
- This is the inverting input of the
error amplifier. It is normally
connected
to
the
switching
PIN 7: VCC -
power supply output through a
resistor divider.
PIN 3: ISENSE - A
voltage
proportional
to
PIN 5: GND-
This pin is the combined control
circuitry and power ground.
PIN 6: OUTPUT- This output directly drives the
gate of a power MOSFET. Peak
currents up to 1A are sourced
and sunk by this pin.
This pin is the positive supply of
the control IC.
PIN 8: VREF -
This is the reference output. It
provides charging current for
capacitor CT through resistor RT.
inductor current is connected to
this input. The PWM uses this
information
to
terminate
the
output switch conduction.
PIN 4: RT/CT
- The
oscillator
frequency
by
and
maximum output duty cycle are
programmed
C
T
to
connecting
Operation
to
resistor R
T
to V
REF
and capacitor
ground.
500KHz is feasible.
5
AIC [ ANALOG INTERGRATIONS CORPORATION ]
