AT1313
High Efficiency, Constant Current
White-LED Driver
V
RIPPLE
=
I
LPEAK
×
ESR
+
V
O
−
V
in
I
O
×
V
O
C
OUT
×
f
OSC
For low ESR ceramic capacitors, the output ripple is dominated by the charging or discharging of the
output capacitor.
PCB layout guidelines
Careful printed circuit layout is extremely important to avoid causing parasitical capacitance and line
inductance. The following layout guidelines are recommended to achieve optimum performance.
‧
Please the boost converter diode and inductor close to the LX pin and no via. Keep traces short,
direct, and wide.
‧
Please ceramic bypass capacitors near the input/output pin.
‧
Locate all feedback sense resistor as close to the feedback pins as possible.
‧
The ground connections of V
IN
and V
OUT
should be as close together as possible.
7F, No.9, PARK AVENUE II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C.
Tel: 886-3-563-0878
Fax: 886-3-563-0879
WWW:
http://www.aimtron.com.tw
10/31/2006 REV:2.0
Email:service@aimtron.com.tw
10
AIMTRON [ AIMTRON TECHNOLOGY ]
