ASAHI KASEI
PIN FUNCTION
Pin types
NIN:
Normal input
AIN:
Analog input
Type
Pin# Name
15
VFTN
AIN
AIN
AOUT
AOUT
AIN
AOUT
PWR
PWR
NIN
TOUT: Try state output
AOUT: Analog output
AK2301A
16
14
7
VFTP
GST
GSR
8
9
6
19
5
VFR
VR
VDD
VSS
FS
3
BCLK
NIN
TOUT
NIN
NIN
NIN
2
DX
4
23
22
DR
MUTEN
RSTN
18
VREF
AOUT
AOUT
20
PLLC
17
TAGND
AOUT
11
12
13
10
21
24
1
AIN
AMP1I
AMP2I
AMP1O
AOUT
Output of the universal OP amp
AMP2O
TEST1
NIN
Test pins
（”H”=test
mode）
Please tie to VSS
TEST2
TEAT3
PWR: Power / Ground
Function
Neagative analog input of the transmit OP amp.
Diffelential or single amplifire is composed with the VFTP and the external
registers. Transmit gain is defined by the ratio of the external registers.
Positive analog input of the transmit OP amp.
Output of the transmit OP amp.
The external feedback resister is connected between this pin and VFTP.
Output of the receive OP amp.
Receive gain is defined by the ratio of the external registers.
The differential output can be composed with using the VR.
Negative analog input of the receive OP amp.
Analog output of the D/A convertor equivalent to the received PCM code.
Positive supply voltage
+3.3V supply
Ground (0V)
Frame sync input
This clock is input for the internal PLL which gerenates the internal system
clocks. FS must be 8kHz clock which synchronized with BCLK and do not stop
feeding.
Bit clock of PCM data interface
This clock defines the input/output timing of DX and RX.
The frequency of BCLK should be 256kHz or 512kHz and do not stop feeding.
Serial output of PCM data
The PCM data is synchronized with BCLK. This output remains in the high
impedance except for the period in which PCM data is transmitted.
Serial input of PCM data
The PCM data is synchronized with BCLK.
Mute setting pin
“L” level forces both A/D, D/A output to mute state.
Reset signal input pin
Reset operation starts by low input. This pin is used for the initialization at the
power up. Please use MUTEN pin together to avoid the popping sound output
until the LSI finish the initialaization after the power up.（Refer to P.13）
Analog ground output
External capacitance (1.0µF or more) should be connected between this pin and
VSS.
Please do not connect external load to this pin.
PLL loop filter output
External capacitance (0.33µF±40%: Includes temperature characteristic) should
be connected between this pin and VSS.
Analog ground output for transmitte OP amp
150uA load max. External capacitance (1.0µF or more) should be connected
between this pin and VSS. This pin is used as an analog ground for transmit OP
amp (AMPT).
Negative input of the universal OP amp
<MS0300-E-00>
4
2004/3
AKM [ ASAHI KASEI MICROSYSTEMS ]
