[AK4127]
PIN/FUNCTION
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Pin Name
FILT
AVSS
PDN
SMUTE
DITHER
PLL2
ILRCK
IBICK
SDTI
IDIF0
IDIF1
IDIF2
PLL0
PLL1
UNLOCK
OBIT0
OBIT1
IMCLK
CMODE0
CMODE1
CMODE2
ODIF0
ODIF1
SDTO
OBICK
OLRCK
OMCLK
DVDD
DVSS
AVDD
I/O
O
-
I
I
I
I
I/O
I/O
I
I
I
I
I
I
O
I
I
I
I
I
I
I
I
O
I/O
I/O
I
-
-
-
Function
PLL Loop Filter Pin, Hi-Z when PDN pin = “L”.
Analog Ground Pin
Power-Down Mode Pin
“H”: Power up, “L”: Power down reset and initializes the control register.
Soft Mute Pin
“H” : Soft Mute, “L” : Normal Operation
Dither Enable Pin
“H” : Dither ON, “L” : Dither OFF
PLL Mode Select 2 Pin
Input Channel Clock Pin, Output “L” when PDN = “L” and master mode.
Audio Serial Data Clock Pin, Output “L” when PDN = “L” and master mode.
Audio Serial Data Input Pin
Audio Interface Format 0 Pin for Input PORT
Audio Interface Format 1 Pin for Input PORT
Audio Interface Format 2 Pin for Input PORT
PLL Mode Select 0 Pin
PLL Mode Select 1 Pin
Unlock Status Pin, Output “H” when PDN = “L”
Bit Length Select 0 Pin for Output Data
Bit Length Select 1 Pin for Output Data
Master Clock Input Pin for Input PORT
Clock Mode Select 0 Pin
Clock Mode Select 1 Pin
Clock Mode Select 2 Pin
Audio Interface Format 0 Pin for Output PORT
Audio Interface Format 1 Pin for Output PORT
Audio Serial Data Output Pin for Output PORT, Output “L” when PDN pin = “L”
Audio Serial Data Clock Pin for Output PORT
Output “L” when PDN = “L” and master mode.
Output Channel Clock Pin for Output PORT
Output “L” when PDN = “L” and master mode.
Master Clock/TDM Data Input Pin for Output PORT
OMCLK: Master Clock Input Pin (except for PLL2/1/0 pin = “L/H/H”)
TDMIN: TDM Data Input Pin (PLL2/1/0 pin = “L/H/H”)
Digital Power Supply Pin, 3.0
∼
3.6V
Digital Ground Pin
Analog Power Supply Pin, 3.0
∼
3.6V
Note: All input pins must not be left floating.
MS0593-E-01
-5-
2007/07
AKM [ ASAHI KASEI MICROSYSTEMS ]
