ASAHI KASEI
[AK4181A]
DC Characteristics (Logic I/O)
Ta=-20 to 70°C, VCC=2.7V to 3.6V
Parameter
“H” level input voltage
“L” level input voltage
Input Leakage Current
“H” level output voltage (@ Iout = -250uA)
“L” level output voltage (@ Iout= 250uA)
Tri-state Leakage Current
All pins except for XP, YP, XN, YN pins
XP, YP, XN, YN pins
PENIRQN “L” level output voltage (100KΩ Pull-Up)
Symbol
VIH
VIL
IILK
VOH
VOL
IOLK
min
0.8xVCC
-10
VCC-0.4
-
-10
-50
VOLP
typ
-
-
-
-
max
0.2xVCC
10
0.4
10
50
0.8
Units
V
V
µA
V
V
µA
µA
V
Switching Characteristics
Ta=-20°C to 70°C, VCC=2.7V to 3.6V
Parameter
Touch Panel (A/D Converter)
Throughput Rate
DCLK
frequency
duty
Tracking Time (Rin=600Ω) (Note 5)
Conversion Time
CSN “↓” to First DCLK “↑”
CSN “↓” to BUSY Tri-State Disabled
CSN “↓” to DOUT Tri-State Disabled
DCLK High Pulse Width
DCLK Low Pulse Width
DCLK “↓” to BUSY “↑”
Data Setup Time
Data Valid to DCLK Hold Time
Data Access Time after DCLK “↓”
CSN “↑” to DCLK Ignored
CSN “↑” to BUSY High-Z state
CSN “↑” to DOUT High-Z state
Symbol
Fs
fDCLK
duty
tTRK
tCONV
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
10
40
1.428
100
200
200
190
190
160
100
10
160
0
200
200
min
typ
max
125
2100
60
12
Units
kHz
kHz
%
µs
1/fDCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
Note 5. The actual tracking periods are 3tDCLK. (tDCLK=1/fDCLK)
CSN
t5
t1
DCLK
t8
t7
DIN
PD0
50%VCC
t4
t6
t6
t9
t10
50%VCC
50%VCC
t2
BUSY
t11
VOH
VOL
t12
t3
DOUT
D11
D10
D0
VOH
VOL
Figure 1 AK4181A Timing Diagram
MS0313-E-00
6
2004/06
AKM [ ASAHI KASEI MICROSYSTEMS ]
