ASAHI KASEI
[AK4358]
SWITCHING CHARACTERISTICS
(Ta = 25
°
C; AVDD, DVDD = 4.75
∼
5.25V; C
L
= 20pF)
Parameter
Symbol
Min
fCLK
2.048
Master Clock Frequency
Duty Cycle
dCLK
40
LRCK Frequency
Normal Mode (TDM0= “L”, TDM1= “L”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
TDM256 mode (TDM0= “H”, TDM1= “L”)
Normal Speed Mode
High time
Low time
TDM128 mode (TDM0= “H”, TDM1= “H”)
Normal Speed Mode
Double Speed Mode
High time
Low time
PCM Audio Interface Timing
BICK Period
BICK Pulse Width Low
Pulse Width High
BICK “
↑
” to LRCK Edge
(Note 16)
LRCK Edge to BICK “
↑
”
(Note 16)
SDTI Hold Time
SDTI Setup Time
DSD Audio Interface Timing
DCLK Period
DCLK Pulse Width Low
Pulse Width High
DCLK Edge to DSDL/R
(Note 17)
Control Interface Timing (3-wire Serial mode):
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN High Time
CSN “
↓
” to CCLK “
↑
”
CCLK “
↑
” to CSN “
↑
”
Control Interface Timing (I
2
C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
(Note 18)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
fsn
fsd
fsq
Duty
fsn
tLRH
tLRL
fsn
fsd
tLRH
tLRL
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
tDCK
tDCKL
tDCKH
tDDD
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
8
60
120
45
32
3/256fs
3/256fs
32
60
3/128fs
3/128fs
81
30
30
20
20
10
10
1/64fs
160
160
-20
200
80
80
40
40
150
50
50
-
4.7
4.0
4.7
4.0
4.7
0
0.25
-
-
4.0
0
Typ
11.2896
Max
36.864
60
Units
MHz
%
48
96
192
55
48
kHz
kHz
kHz
%
kHz
ns
ns
kHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
48
96
20
100
-
-
-
-
-
-
-
1.0
0.3
-
50
kHz
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
ns
MS0203-E-01
-8-
2006/02
AKM [ ASAHI KASEI MICROSYSTEMS ]
