ASAHI KASEI
[AK4620B]
PIN/FUNCTION
No.
1
2
3
4
5
Pin Name
VCOM
AINR+
AINR-
AINL+
AINL-
I/O
O
I
I
I
I
I
I
Function
Common Voltage Output Pin, VA/2
Bias voltage of ADC inputs and DAC outputs.
Rch Positive Input Pin
Rch Negative Input Pin (when ADMODE pin=“H”)
No Connect pin (when ADMODE pin=“L”)
No internal bonding. This pin should be open.
Lch Positive Input Pin
Lch Negative Input Pin (when ADMODE pin=“H”)
No Connect pin (when ADMODE pin=“L”)
No internal bonding. This pin should be open.
Voltage Reference Input Pin, VA
Used as a voltage reference by ADC & DAC. VREF is connected externally to filtered
VA.
Analog Ground Pin
Analog Power Supply Pin, 4.75
∼
5.25V
Parallel/Serial Mode Select Pin
“L”: Serial Mode, “H”: Parallel Mode
Do not change this pin during PDN pin = “H”.
Master Clock Input Pin
Input/Output Channel Clock Pin (in Parallel mode or when D/P bit=“0” in Serial Mode)
DSD Rch Data Input Pin (when D/P bit=“1” in Serial Mode)
Audio Serial Data Clock Pin (in Parallel mode or when D/P bit=“0” in Serial Mode)
DSD Clock Pin (when D/P bit=“1” in Serial Mode)
Audio Serial Data Output Pin
Audio Serial Data Input Pin (in Parallel mode or when D/P bit=“0” in Serial Mode)
DSD Lch Data Input Pin (when D/P bit=“1” in Serial Mode)
Rch Over Flow Flag Pin (in Parallel mode or when ZOS bit=“0” in Serial Mode)
Rch Zero Detection Flag Pin (when ZOS bit=“1” in Serial Mode)
Lch Over Flow Flag Pin (in Parallel mode or when ZOS bit=“0” in Serial Mode)
Lch Zero Detection Flag Pin (when ZOS bit=“1” in Serial Mode)
Control Data Input Pin (in Serial Mode)
Master Clock Select Pin (in Parallel Mode)
Control Data Clock Pin (in Serial Mode)
Master Clock Select Pin (in Parallel Mode)
Chip Select Pin in Serial Mode (in Serial Mode)
Digital Audio Interface Select Pin (in Parallel Mode)
“L”: 24bit MSB justified, “H”: I
2
S compatible
Double Speed Sampling Mode Pin
Power-Down Mode Pin
“L”: Power down reset and initialize the control register, “H”: Power up
De-emphasis Control Pin
Analog Input Mode Select Pin
“L”: Single-ended Input & IPGA Enable
“H”: Differential Input & IPGA Bypass
6
7
8
9
10
11
12
13
14
15
16
17
18
VREF
AGND
VA
P/S
MCLK
LRCK
DSDR
BICK
DCLK
SDTO
SDTI
DSDL
OVFR
DZFR
OVFL
DZFL
CDTI
CKS0
CCLK
CKS1
CSN
I
-
-
I
I
I
I
I
I
O
I
I
O
O
O
O
I
I
I
I
I
I
I
I
I
I
19
20
21
22
23
DIF
DFS0
PDN
DEM0
ADMODE
MS0401-E-00
-4-
2005/07
AKM [ ASAHI KASEI MICROSYSTEMS ]
