ASAHI KASEI
[AK5380]
SWITCHING CHARACTERISTICS (fs=48kHz∼96kHz)
(Ta=-40∼85°C; VA=4.5∼5.5V; VD=4.5∼5.5V; C
L
=20pF)
Parameter
Symbol
Control Clock Frequency
Master Clock 256fs:
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
384fs:
fCLK
Pulse Width Low
fCLKL
Pulse Width High
fCLKH
SCLK Frequency
fSLK
LRCK Frequency
fs
Serial Interface Timing
(Note 12)
tSLK
SCLK Period
tSLKL
SCLK Pulse Width Low
tSLKH
Pulse Width High
tLRSH
LRCK Edge to SCLK “↑”
(Note 13)
tSHLR
SCLK “↑” to LRCK Edge
(Note 13)
tDLR
LRCK Edge to SDTO Valid (Note 14)
tDSS
SCLK “↓” to SDTO Valid
Power-Down & Reset Timing
PDN Pulse Width
tPDW
tPDV
PDN “↑” to SDTO delay
(Note 15)
min
12.288
16
16
18.432
11
11
48
160
65
65
30
30
20
20
150
4129
typ
max
24.576
Units
MHz
ns
ns
MHz
ns
ns
MHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
1/fs
36.864
6.144
96
Notes:
12. Refer to the operating overview section “Serial Data Interface”.
13. SCLK rising edge must not occur at the same time as LRCK edge.
14. In case of MSB justified format.
15. These cycles are the number of LRCK rising from PDN rising.
MS0100-E-01
-9-
2001/7
AKM [ ASAHI KASEI MICROSYSTEMS ]
