ASAHI KASEI
[AK6480C/81]
Read
The read instruction is the only instruction which outputs serial data on the DO pin. When the
17th falling edge of SK is received , the DO pin will come out of high impedance state and shift
out the data from D15 (AK6481C: D0) first in descending order which is located at the address
specified in the instruction.
The data in the next address can be read sequentially by continuing to provide clock. The
address automatically cycles to the next higher address after the 16bit data shifted out. When the
highest address is reached (A8-A0 : 1 1111 1111), the address counter rolls over to address
(A8-A0 : 0 0000 0000) allowing the read cycle to be continued indefinitely.
CS
SK
DI
DO
RDY/
BUSY
* The data in the next address can be read sequentially by continuing to provide clock.
1
2
3
4
5
6
7
8
9
10
15
16
17
18
32
33
34
48
1
0
1
0
1
0
0
A8
Hi-Z
A7
A6
A1
A0
D15 D14
D0 D15 D14
*
D0
"H"
READ (AK6480C)
CS
SK
DI
DO
RDY/
BUSY
* The data in the next address can be read sequentially by continuing to provide clock.
1
2
3
4
5
6
7
8
9
10
15
16
17
18
32
33
34
48
1
0
1
0
1
0
0
A0
Hi-Z
A1
A2
A7
A8
D0 D1
D15 D0 D1
*
D15
"H"
READ (AK6481C)
WREN / WRDS
( Write Enable and Write Disable )
When VCC is applied to the part, it powers up in the programming disable (WRDS) state.
Programming must be preceded by a programming enable (WREN) instruction. Programming
remains enabled until a programming disable (WRDS) instruction is executed or VCC is removed
from the part. The programming disable instruction is provided to protect against accidental data
disturb. Execution of a read instruction is not affected by both WREN and WRDS instructions.
CS
SK
DI
DO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
0
1
0
0
0
WREN=11
WRDS=00
X
X
Hi-Z
X
X
X
X
X
X
SK pulses exceeding 17 are ignored.
WREN / WRDS
DAS04E-00
- 8 -
2005/03
AKM [ ASAHI KASEI MICROSYSTEMS ]
