ASAHI KASEI
E7
D6
B3
G7
B7
D2
D1
E2
E1
F2
C3
A1, A7,
G1
PVDD
PVSS
BVSS
TEST
ATPG
UD4
UD3
UD2
UD1
UD0
N.C.
N.C.
P
G
G
I
I
O
O
O
I/O
I/O
-
-
Power supply pin for chip pad.
Ground pin for PVDD.
Substrate ground pin.
Connect this pin to Analog ground
For normal operation, connect to ground.
For normal operation, connect to ground.
Test output pin. For normal operation, left open.
Test output pin. For normal operation, left open.
Test output pin. For normal operation, left open.
Test I/O pin. For normal operation, left open.
Test I/O pin. For normal operation, left open.
Index pin. For normal operation, left open.
For normal operation, left open.
[AK8817/18]
Rev.001E
6
2009 / 12
AKM [ ASAHI KASEI MICROSYSTEMS ]
