APPLICATIONS AND DESIGN NOTES
Determination and Selection of System Variables
The procedure outlined below allows the user to determine the
values for the following ALD500RAU/ALD500RA/ALD500R
system design variables:
(1)
(2)
(3)
(4)
(5)
(6)
Determine Input Voltage Range
Clock Frequency and Resolution Selection
Input Integration Phase Timing
Integrator Timing Components (R
INT
, C
INT
)
Auto Zero and Reference Capacitors
Voltage Reference
where:
V
IN
MAX = Maximum input voltage desired
(full count voltage)
R
INT
= Integrating Resistor value
For minimum noise and maximum linearity, R
INT
should be in
the range of between 50kΩ to 150kΩ .
Integrating Capacitor (C
INT
)
The integrating capacitor should be selected to maximize
integrator output voltage swing V
INT
, for a given integration
time, without output level saturation. For +/-5V supplies,
recommended V
INT
range is between +/- 3 Volt to +/-4 Volt.
Using the 20µA buffer maximum output current, the value of
the integrating capacitor is calculated as follows:
C
INT
= (t
INT
) . (20 x 10
-6
) / V
INT
where: t
INT
=
V
INT
=
Input Integration Phase Period
Maximum integrator output
voltage swing
System Timing
Figure 3 and Figure 4 show the overall timing for a typical
system in which ALD500RAU/ALD500RA/ALD500R is
interfaced to a microcontroller. The microcontroller drives the
A, B inputs with I/O lines and monitors the comparator output,
C
OUT
, using an I/O line or dedicated timer-capture control pin.
It may be necessary to monitor the state of the comparator
output in addition to having it control a timer directly during the
Reference Deintegration Phase.
There are four critical timing events: sampling the input
polarity; capturing the deintegration time; minimizing overshoot
and properly executing the Integrator Output Zero Phase.
Selecting Input Integration Time
For maximum 50/60 cycle noise rejection, Input Integration
Time must be picked as a multiple of the period of line
frequency. For example, t
INT
times of 33msec, 66msec and
100 msec maximize 60Hz line rejection, and 20msec, 40
msec, 80msec, and 100 msec maximize 50Hz line rejection.
Note that t
INT
of 100 msec maximizes both 60 Hz and 50Hz
line rejection.
INT and D
INT
Phase Timing
The duration of the Reference Deintegrate Phase (D
INT)
is a
function of the amount of voltage charge stored on the
integrator capacitor during INT phase, and the value of V
REF
.
The D
INT
phase must be initiated immediately following INT
phase and terminated when an integrator output zero-crossing
is detected. In general, the maximum number of counts
chosen for D
INT
phase is twice to three times that of INT phase
with V
REF
chosen as a maximum voltage relative to V
IN
. For
example, V
REF
= V
IN
(max)/2 would be a good reference
voltage.
Integrating Resistor (R
INT
)
The desired full-scale input voltage and amplifier output
current capability determine the value of R
INT
. The buffer and
integrator amplifiers each have a full-scale current of 20µA.
The value of R
INT
is therefore directly calculated as follows:
R
INT
= V
IN
MAX / 20
µA
It is critical that the integrating capacitor must have a very low
dielectric absorption, as charge loss or gain during conversion
directly converts into an error voltage. Polypropylene capacitors
are recommended while Polyester and Polybicarbonate
capacitors may also be used in less critical applications.
Reference (C
REF
) and Auto Zero (C
AZ
) Capacitors
C
REF
and C
AZ
must be low leakage capacitors (e.g.
polypropylene types). The slower the conversion rate, the
larger the value C
REF
must be. Recommended capacitor
values for C
REF
and C
AZ
are equal to C
INT
. Larger values for
C
AZ
and C
REF
may also be used to limit roll-over errors.
Calculate V
REF
The reference deintegration voltage is calculated using:
V
REF
= (V
INT
) . (C
INT
) . (R
INT
) / 2(t
INT
)
The ALD500RAU/ALD500RA/ALD500R requires an external
R
REF
in order to operate properly. This R
REF
should be a 1%
metal film 100KΩ resistor, 50 ppm/C. Any other loading must
be high impedance (≥100MΩ).
Converter Noise
The converter noise is the total algebraic sum of the integrator
noise and the comparator noise. This value is typically 14
µV
peak to peak. The higher the value of the reference voltage,
the lower the converter noise. Such sources of noise errors
can be reduced by increased integration times, which effectively
filter out any such noise. If the integration time periods are
selected as multiples of 50/60Hz frequencies, then 50/60Hz
noise is also rejected, or averaged out. The signal-to-noise
ratio is related to the integration time (t
INT
) and the integration
time constant (R
INT
) (C
INT
) as follows:
S/N (dB) = 20 Log ((V
INT
/ 14 x 10
-6
) . t
INT
/(R
INT
. C
INT
))
This converter noise can also be reduced by using multiple
samples and mathematically averaged. For example, taking
16 samples and averaging the readings result in a mathematical
(by software) filtering of noise to less than 4µV.
10
Advanced Linear Devices
ALD500RAU/ALD500RA/ALD500R
ALD [ ADVANCED LINEAR DEVICES ]
