Page 6
3932
THREE-PHASE POWER MOSFET CONTROLLER
PIN DESCRIPTIONS (continued)
VREG.
Regulated 13 V output supply for low side gate
drive and bootstrap capacitor charge circuit. It is good
practice to connect a decoupling capacitor from this pin to
AGND, as close to the device pins as possible. Pin should be
shorted to VBB for 12V applications.
DEAD.
Analog input. A resistor between DEAD and LCAP
is selected to adjust turn-off to turn-on time. This delay is
needed to prevent shoot-thru in the external power FET’s.
The resistor allowable range is 5.6k to 470k, which converts
to deadtime of 100ns to 5500ns.
T
DEAD
≅
11e-12 * R
DEAD
V
BB
.
Motor power supply connection for A3932 and power
MOSFETs. Pin should be shorted to VREG for 12V
applications.
AGND.
Analog reference.
PGND.
Return for low side gate drive. This should be
connected to PCB power ground.
REF.
Analog input to current limit comparator. Voltage
applied here sets the peak load current according to the
equation:
I
TRIP
= V
REF
/R
SENSE
LCAP.
5V reference to power internal logic, connection for
decoupling cap. This pin requires 1nF external capacitor for
decoupling and should not be used to power any external
circuitry.
Commutation Truth Table
H1
1
1
1
0
0
0
1
1
1
0
0
0
H2
0
0
1
1
1
0
0
0
1
1
1
0
H3
1
0
0
0
1
1
1
0
0
0
1
1
DIR
1
1
1
1
1
1
0
0
0
0
0
0
GLA
0
0
1
1
0
0
1
0
0
0
0
1
GLB
0
0
0
0
1
1
0
1
1
0
0
0
GLC
1
1
0
0
0
0
0
0
0
1
1
0
GHA
1
0
0
0
0
1
0
0
1
1
0
0
GHB
0
1
1
0
0
0
0
0
0
0
1
1
GHC
0
0
0
1
1
0
1
1
0
0
0
0
SA
HI
Z
LO
LO
Z
HI
LO
Z
HI
HI
Z
LO
SB
Z
HI
HI
Z
LO
LO
Z
LO
LO
Z
HI
HI
SC
LO
LO
Z
HI
HI
Z
HI
HI
Z
LO
LO
Z
INPUT LOGIC
MODE
0
0
1
1
0
0
1
1
X
PWM
0
1
0
1
0
1
0
1
X
S/R
0
0
0
0
1
1
1
1
X
RESET
0
0
0
0
0
0
0
0
1
Quadrant
Fast decay
Fast Decay
Slow decay
Slow Decay
Fast decay
Fast Decay
Slow decay
Slow Decay
X
Mode of Operation
PWM chop– current decay, all drivers off
Peak Current limit – selected drivers ON
PWM chop – current decay, selected Low side ON
Peak Current limit mode – selected drivers ON
PWM chop – current decay with opposite of selected drivers ON
Peak Current limit – selected drivers ON
PWM chop – current decay with both Low side drivers ON
Peak Current limit – selected drivers ON
All gate drive outputs to 0V – Clear fault logic
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