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A3950SEUTR-T 参数 Datasheet PDF下载

A3950SEUTR-T图片预览
型号: A3950SEUTR-T
PDF下载: 下载PDF文件 查看货源
内容描述: DMOS全桥式电动机驱动器 [DMOS Full-Bridge Motor Driver]
分类和应用: 驱动器运动控制电子器件信号电路电动机控制
文件页数/大小: 12 页 / 531 K
品牌: ALLEGRO [ ALLEGRO MICROSYSTEMS ]
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A3950
DMOS Full-Bridge Motor Driver
Features and Benefits
Low R
DS(on)
outputs
Overcurrent protection
Motor lead short-to-supply protection
Short-to-ground protection
Sleep function
Synchronous rectification
Diagnostic output
Internal undervoltage lockout (UVLO)
Crossover-current protection
Description
Designed for PWM (pulse width modulated) control of dc
motors, the A3950 is capable of peak output currents to ±2.8 A
and operating voltages to 36 V.
PHASE and ENABLE input terminals are provided for use in
controlling the speed and direction of a dc motor with externally
applied PWM control signals. Internal synchronous rectification
control circuitry is provided to lower power dissipation during
PWM operation.
Internal circuit protection includes motor lead short-to-
supply / short-to-ground, thermal shutdown with hysteresis,
undervoltage monitoring of V
BB
and V
CP
, and crossover-current
protection.
Package EU, 16 pin QFN
with Exposed Thermal Pad
Packages:
Package LP, 16 pin TSSOP
with Exposed Thermal Pad
The A3950 is supplied in a thin profile (<1.2 mm overall height)
16 pin TSSOP package (LP), and a very thin (0.75 mm nominal
height) QFN package. Both packages provide an exposed pad
for enhanced thermal dissipation, and are lead (Pb) free with
100% matte tin leadframe plating.
Approximate Scale 1:1
Typical Application Diagrams
V
BB
0.1
μF
50 V
NFAULT
GND
CP2
CP1
OUTB
SENSE
OUTA
VBB
NC
0.1
μF
50 V
100
μF
50 V
NC
VREG
VCP
0.1
μF
50 V
0.22
μF
25 V
0.22
μF
25 V
V
BB
NFAULT
MODE
V
DD
5 kΩ
PHASE
GND
SLEEP
ENABLE
VREG
VCP
V
DD
5 kΩ
MODE
PHASE
GND
SLEEP
ENABLE
OUTA
SENSE
A3950
EU Package
A3950
LP Package
GND
CP2
CP1
OUTB
VBB
0.1
μF
50 V
0.1
μF
50 V
100
μF
50 V
0.1
μF
50 V
Package EU
Package LP
A3950DS, Rev. 4