3951
FULL-BRIDGE
PWM MOTOR DRIVER
FUNCTIONAL BLOCK DIAGRAM
PHASE
UVLO
& TSD
ENABLE
REF/BRAKE
+
–
R
S
SENSE
RC
Q
9R
BLANKING
R
1.5 V
S
PWM LATCH
V
CC
+
–
V
R
TH
GROUND
Dwg. FP-036-1
10
SUFFIX 'W',
R
= 2.0°C/W
θJT
8
6
SUFFIX 'B',
R
= 6.0°C/W
θJT
TRUTH TABLE
BRAKE ENABLE PHASE
OUTA
OUTB
DESCRIPTION
Outputs Disabled
Forward
4
2
0
H
H
H
H
L
X
H
L
Z
H
L
Z
L
SUFFIX 'W', R
= 38°C/W
θJA
L
H
L
Reverse
SUFFIX 'B', R
= 43°C/W
θJA
L
X
X
L
Brake, See Note
X = Irrelevant
Z = High Impedance (source and sink both off)
25
50
75
100
125
150
NOTE: Includes internal default Vsense level for over-current protection.
TEMPERATURE IN °C
Dwg. GP-032A
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1994, 2000 Allegro MicroSystems, Inc.
2
ALLEGRO [ ALLEGRO MICROSYSTEMS ]
