A3955
Full-Bridge PWM Microstepping Motor Driver
which turns off the source drivers (slow-decay mode) or the sink
and source drivers (fast- or mixed-decay mode).
With the DATA input lines tied to V
CC
, the maximum value of
current limiting is set by the selection of R
S
and V
REF
with a
transconductance function approximated by:
I
TRIP
≈
V
REF
/ 3R
S
.
The actual peak load current (I
PEAK
) will be slightly higher than
I
TRIP
due to internal logic and switching delays. The driver(s)
remain off for a time period determined by a user-selected
external resistor-capacitor combination (R
T
C
T
). At the end of
the
fi
xed off-time, the driver(s) are re-enabled, allowing the load
current to increase to I
TRIP
again, maintaining an average load
current.
The DAC data input lines are used to provide up to eight levels
of output current. The internal 3-bit digital-to-analog converter
reduces the reference input to the current-sense comparator
in precise steps (the step reference current ratio or SRCR) to
provide half-step, quarter-step, or “microstepping” load-current
levels.
I
TRIP
≈
SRCR x V
REF
/3R
S
Functional Description
Two A3955 full-bridge PWM microstepping motor drivers are
needed to drive the windings of a bipolar stepper motor. Internal
pulse width modulated (PWM) control circuitry regulates each
motor winding current. The peak motor current is set by the
value of an external current-sense resistor (R
S
), a reference
voltage (V
REF
), and the digital-to-analog converter (DAC) data
inputs (D
0
, D
1
, and D
2
).
To improve motor performance, especially when using
sinusoidal current profiles necessary for microstepping, the
A3955 has three distinct current-decay modes: slow decay, fast
decay, and mixed decay.
PHASE Input.
The PHASE input controls the direction of
current
fl
ow in the load (table 1). An internally generated dead
time of approximately 1
μs
prevents crossover currents that
could occur when switching the PHASE input.
to digitally control the output current. The output of the DAC is
used to set the trip point of the current-sense comparator. Table 3
shows DAC output voltages for each input condition. When D
0
,
D
1
, and D
2
are all logic low, all of the power output transistors
are turned off.
DAC Data Inputs (D
0
, D
1
, D
2
).
A non-linear DAC is used
Slow Current-Decay Mode.
When V
PFD
≥
3.5 V, the
device is in slow current-decay mode (the source drivers are
disabled when the load current reaches I
TRIP
). During the
fi
xed
off-time, the load inductance causes the current to recirculate
through the motor winding, sink driver, ground clamp diode,
and sense resistor (see
fi
gure 1). Slow-decay mode produces
low ripple current for a given
fi
xed off-time (see
fi
gure 2).
Low ripple current is desirable because the average current
in the motor winding is more nearly equal to the desired
Internal PWM Current Control.
Each motor driver
contains an internal
fi
xed off-time PWM current-control circuit
that limits the load current to a desired value (I
TRIP
). Initially,
a diagonal pair of source and sink transistors are enabled and
current
fl
ows through the motor winding and R
S
(figure 1). When
the voltage across the sense resistor equals the DAC output
voltage the current-sense comparator resets the PWM latch,
V
BB
I
PEAK
SLOW (V
PFD
≥
3.5 V)
MIXED (1.1 V
≤
V
PFD
≤
3.1 V)
DRIVE CURRENT
RECIRCULATION
(SLOW-DECAY MODE)
RECIRCULATION
(FAST-DECAY MODE)
PFD
FAST (V
PFD
≤
0.8 V)
t
OFF
Dwg. WP-031-1
RS
Dwg. EP-006-15
Figure 1 — Load-Current Paths
Figure 2 — Current-Decay Waveforms
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
ALLEGRO [ ALLEGRO MICROSYSTEMS ]
