3958
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
FUNCTIONAL DESCRIPTION
(continued)
V
REG
.
This internally generated voltage is used to operate
the sink-side DMOS outputs. The V
REG
terminal should
be decoupled with a 0.22
µF
capacitor to ground. V
REG
is
internally monitored and in the case of a fault condition,
the outputs of the device are disabled.
Charge Pump.
The charge pump is used to generate a
gate-supply voltage greater than V
BB
to drive the source-
side DMOS gates. A 0.22
µF
ceramic capacitor should be
connected between CP1 and CP2 for pumping purposes.
A 0.22
µF
ceramic capacitor should be connected between
CP and V
BB
to act as a reservoir to operate the high-side
DMOS devices. The CP voltage is internally monitored
and, in the case of a fault condition, the source outputs of
the device are disabled.
Shutdown.
In the event of a fault (excessive junction
temperature, or low voltage on CP or V
REG
) the outputs of
the device are disabled until the fault condition is
removed. At power up, and in the event of low V
DD
, the
UVLO circuit disables the drivers and resets the data in
the serial port to all zeros.
PWM Timer Function.
The PWM timer is
programmable via the serial port (bits D2 – D10) to
provide off-time PWM signals to the control circuitry. In
the mixed current-decay mode, the first portion of the off
time operates in fast decay, until the fast decay time count
(serial bits D7 – D10) is reached, followed by slow decay
for the rest of the off-time period (bits D2 – D6). If the
fast decay time is set longer than the off time, the device
effectively operates in fast decay mode. Bit D17, in
conjunction with MODE, selects mixed or slow decay.
PWM Blank Timer.
When a source driver turns on, a
current spike occurs due to the reverse recovery currents
of the clamp diodes and/or switching transients related to
distributed capacitance in the load. To prevent this current
spike from erroneously resetting the source-enable latch,
the sense comparator is blanked. The blank timer runs
after the off-time counter (see bits D2 – D6) to provide the
programmable blanking function. The blank timer is reset
when ENABLE is chopped or PHASE is changed. For
external PWM control, a PHASE change or ENABLE on
will trigger the blanking function.
Synchronous Rectification.
When a PWM off cycle
is triggered, either by an ENABLE chop command or
internal fixed off-time cycle, load current will recirculate
according to the decay mode selected by the control logic.
The A3958 synchronous rectification feature will turn on
the opposite pair of DMOS outputs during the current
decay and effectively short out the body diodes with the
low r
DS(on)
driver. This will reduce power dissipation
significantly and can eliminate the need for external
Schottky diodes.
Synchronous rectification can be configured in active
mode, passive mode, or disabled via the serial port (bits
D11 and D12).
The active or passive mode selection has no impact in
slow-decay mode. With synchronous rectification
enabled, the slow-decay mode serves as an effective brake
mode.
Current Regulation.
Load current is regulated by an
internal fixed off-time PWM control circuit. When the
outputs of the DMOS H bridge are turned on, the current
increases in the motor winding until it reaches a trip value
determined by the external sense resistor (R
S
), the applied
analog reference voltage (V
REF
), the RANGE logic level,
and serial data bit D16:
When RANGE = D16 ........... I
TRIP
= V
REF
/10R
S
When RANGE
≠
D16 ........... I
TRIP
= V
REF
/5R
S
At the trip point, the sense comparator resets the source-
enable latch, turning off the source driver. The load
inductance then causes the current to recirculate for the
serial-port-programmed fixed off-time period. The
current path during recirculation is determined by the
configuration of slow/mixed current-decay mode (D17)
and the synchronous rectification control bits (D11 and
D12).
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