3967
MICROSTEPPING DRIVER
WITH TRANSLATOR
FUNCTIONAL BLOCK DIAGRAM
LOGIC
SUPPLY
V
CC
REF.
SUPPLY
REF
1
14
LOAD
SUPPLY
UVLO
AND
FAULT
DETECT
V
BB1
20
÷8
DAC
+
-
SENSE
RC
1
23
PWM LATCH
BLANKING
MIXED DECAY
OUT
1A
16
OUT
1B
21
3
STEP
10
PWM TIMER
TRANSLATOR
DIR
11
RESET
22
MS
1 12
MS
2 13
SENSE
1
CONTROL LOGIC
17
5
V
BB2
SLEEP
3
ENABLE
15
V
PF
24
OUT
2A
PWM TIMER
3
PWM LATCH
BLANKING
MIXED DECAY
9
PFD
2
OUT
2B
4
RC
2
+
DAC
6
7
18 19
-
8
SENSE
2
Dwg. FP-050-3A
Table 1. Microstep Resolution Truth Table
MS
1
L
H
L
H
MS
2
L
L
H
H
Resolution
Full step (2 phase)
Half step
Quarter step
Eighth step
2
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Copyright © 2002, 2003 Allegro MicroSystems, Inc.