3972
DUAL DMOS FULL-BRIDGE
MICROSTEPPING PWM MOTOR DRIVER
FUNCTIONAL BLOCK DIAGRAM
0.22
µF
0.22
µF
22
V
REG
3
CP2
2
CP1
LOGIC
SUPPLY
2V
15
V
DD
UVLO AND
FAULT
DETECT
REGULATOR
BANDGAP
V
CP
LOAD
SUPPLY
CHARGE PUMP
1
V
BB1
MUX
14
5
0.22
µF
6-BIT
LINEAR
DAC
+
6
DMOS H-BRIDGE
SENSE
1
V
CP
-
OUT
1A
9
OSCILATOR
OSC
24
PROGRAMMABLE
PWM TIMER
FIXED-OFF
BLANK
MIXED DECAY
OUT
1B
4
OSC SELECT/
DIVIDER
SENSE
1
8
CLOCK
11
DATA
12
STROBE
10
SERIAL
PORT
CONTROL
LOGIC
PHASE 1/2
SYNC. RECT. MODE
SYNC. RECT. DISABLE
MODE 1/2
GATE
DRIVE
DMOS H-BRIDGE
0.1
µF
20
V
BB2
SLEEP
23
OUT
2A
16
PROGRAMMABLE
PWM TIMER
2V
6
FIXED-OFF
BLANK
MIXED DECAY
OUT
2B
21
REF
13
BUFFER
+
6-BIT
LINEAR
DAC
-
SENSE
2
17
0.1
µF
6
GROUND
7
18 19
Dwg. FP-050-1
2
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Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 2000, Allegro MicroSystems, Inc.
ALLEGRO [ ALLEGRO MICROSYSTEMS ]
