3977
MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR
FUNCTIONAL BLOCK DIAGRAM
LOGIC
SUPPLY
V
DD
REF.
SUPPLY
REF
UVLO
AND
FAULT
2V
REGULATOR
BANDGAP
V
REG
CP
2
CHARGE
PUMP
CP
1
V
CP
LOAD
SUPPLY
V
BB1
DMOS H BRIDGE
DAC
+ -
SENSE
1
V
CP
RC
1
PWM LATCH
BLANKING
MIXED DECAY
OUT
1A
OUT
1B
4
STEP
PWM TIMER
MS
1
MS
2
HOME
SLEEP
V
PFD
SR
CONTROL LOGIC
GATE DRIVE
RESET
TRANSLATOR
DIR
SENSE
1
DMOS H BRIDGE
V
BB2
OUT
2A
OUT
2B
ENABLE
PWM TIMER
PFD
4
PWM LATCH
BLANKING
MIXED DECAY
RC
2
DAC
+
-
SENSE
2
Dwg. FP-050-2
2
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 2002, 2003 Allegro MicroSystems, Inc.