A3979
Microstepping DMOS Driver with Translator
Features and Benefits
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±2.5 A, 35 V output rating
Low R
DS(On)
outputs: 0.28
Ω
source, 0.22
Ω
sink, typical
Automatic current decay mode detection/selection
3.0 to 5.5 V logic supply voltage range
Slow, Fast or Mixed current decay modes
Home output
Synchronous rectification for low power dissipation
Internal UVLO and thermal shutdown circuitry
Crossover-current protection
Description
The A3979 is a complete microstepping motor driver with
built-in translator, designed as a pin-compatible replacement for
the successful A3977, with enhanced microstepping (
1
/
16
step)
precision. It is designed to operate bipolar stepper motors in
full-, half-, quarter-, and sixteenth-step modes, with an output
drive capacity of up to 35 V and ±2.5 A. The A3979 includes a
fixed off-time current regulator that has the ability to operate in
Slow, Fast, or Mixed decay modes. This current-decay control
scheme results in reduced audible motor noise, increased step
accuracy, and reduced power dissipation.
The translator is the key to the easy implementation of the
A3979. It allows the simple input of one pulse on the STEP
pin to drive the motor one microstep, which can be either a full
step, half, quarter, or sixteenth, depending on the setting of the
MS1 and MS2 logic inputs. There are no phase-sequence tables,
high-frequency control lines, or complex interfaces to program.
The A3979 interface is an ideal fit for applications where a
complex microprocessor is unavailable or is overburdened.
Internal synchronous-rectification control circuitry is provided
to improve power dissipation during PWM operation. Internal
circuit protection includes: thermal shutdown with hysteresis,
UVLO (undervoltage lockout), and crossover-current
protection. Special power-on sequencing is not required.
Package: 28 lead TSSOP (suffix LP) with
exposed thermal pad
Not to scale
The A3979 is supplied in a low-profile (height
≤1.20
mm),
28-pin TSSOP with exposed thermal pad. The package is lead
(Pb) free, with 100% matte tin leadframe plating.
Pin-out Diagram
SENSE1 1
HOME 2
DIR 3
OUT1A 4
PFD 5
RC1 6
AGND 7
REF 8
RC2 9
VDD 10
OUT2A 11
MS2 12
MS1 13
SENSE2 14
÷8
PWM
Timer
Charge
Pump
28 VBB1
27 SLEEP
26 ENABLE
25 OUT1B
24 CP2
Translator
and
Control
Logic
23 CP1
22 VCP
21 PGND
Reg
20 VREG
19 STEP
18 OUT2B
17 RESET
16 SR
15 VBB2
and
PGND
must be
connected together externally
AGND
26184.23D
ALLEGRO [ ALLEGRO MICROSYSTEMS ]
