A3995
DMOS Dual Full Bridge PWM Motor Driver
EV Package, 36 Pin QFN with Exposed Thermal Pad
Preliminary dimensions, for reference only
(reference JEDEC MO-220VJJD-1, except exposed thermal pad)
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference IPC7351
QFN50P600X600X100-37V1M); adjust as necessary to
meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal
vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
6.15 .242
5.85 .230
36
A
A
B
1
2
6.15 .242
5.85 .230
36X
0.08 [.003] C
36X
0.30 .012
0.18 .007
0.10 [.004] M C A B
0.05 [.002] M C
0.50 .020
SEATING
PLANE
1.00 .039
0.80 .031
0.20 .008
REF
0.05 .002
0.00 .000
C
0.25 .010
NOM
1.15 .045
NOM
1
2
4X0.20 .008
MIN
36
32X0.20 .008
MIN
0.50 .020
NOM
0.75 .030
0.35 .014
C
4.15 .163
NOM
5.8 .228
NOM
R0.30 .012
REF
2
1
36
4.15 .163
NOM
4.15 .163
NOM
4X0.20 .008
MIN
4.15 .163
NOM
5.8 .228
NOM
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
Copyright© 2006 AllegroMicrosystems, Inc.
For the latest version of this document, visit our website:
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
9
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