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• Organization: 512Kx8/256Kx16
• Sector architecture
- One 16K; two 8K; one 32K; and seven 64K byte sectors
- One 8K; two 4K; one 16K; and seven 32K word sectors
- Boot code sector architecture—T (top) or B (bottom)
- Erase any combination of sectors or full chip
• Single 2.7-3.6V power supply for read/write operations
• Sector protection
• High speed 70/80/90/120 ns address access time
• Automated on-chip programming algorithm
- Automatically programs/verifies data at specified address
• Automated on-chip erase algorithm
- Automatically preprograms/erases chip or specified
sectors
• Hardware
RE S E T
pin
- Resets internal state machine to read mode
• Low power consumption
- 200 nA typical automatic sleep mode current
- 200 nA typical standby current
- 10 mA typical read current
• JEDEC standard software, packages and pinouts
- 48-pin TSOP
- 44-pin SO; availability TBD
• Detection of program/erase cycle completion
- DQ7
DATA
polling
- DQ6 toggle bit
- DQ2 toggle bit
- RY/
BY
output
• Erase suspend/resume
- Supports reading data from or programming data
to a sector not being erased
• Low V
CC
write lock-out below 1.5V
• 10 year data retention at 150C
• 100,000 write/erase cycle endurance
DQ0–DQ15
/RJLF EORFN GLDJUDP
RY/BY
V
CC
V
SS
Sector protect/
erase voltage
switches
Erase voltage
generator
RESET
WE
BYTE
Command
register
Program/erase
control
Input/output
buffers
Program voltage
generator
Chip enable
Output enable
Logic
STB
Data latch
CE
OE
A-1
V
CC
detector
Timer
Address latch
STB
Y decoder
Y gating
X decoder
Cell matrix
A0–A17
6HOHFWLRQ JXLGH
Maximum access time
Maximum chip enable access time
Maximum output enable access time
t
AA
t
CE
t
OE
29LV400-70
70
70
30
29LV400-80
80
80
30
29LV400-90
90
90
35
29LV400-120
120
120
50
Unit
ns
ns
ns
9/26/01; V.0.9.9.2
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ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
