High Performance
1M×4
CMOS DRAM
AS4C14400
AS4C14405
®
1M-bit × 4 CMOS DRAM (Fast page mode or EDO)
Preliminary information
Features
• Organization: 1,048,576 words × 4 bits
• High speed
- 40/50/60/70 ns RAS access time
- 20/25/30/35 ns column address access time
- 10/13/15/18 ns CAS access time
• 1024 refresh cycles, 16 ms refresh interval
- RAS-only or CAS-before-RAS refresh
• Read-modify-write
• TTL-compatible, three-state I/O
• JEDEC standard packages
- 300 mil, 20/26-pin SOJ
- 300 mil, 20/26-pin TSOP
• Low power consumption
- Active: 385 mW max (-60)
- Standby: 5.5 mW max, CMOS I/O
• Fast page mode (AS4C14400) or EDO (AS4C14405)
• Single 5V power supply
• ESD protection
≥
2001V
• Latch-up current
≥
200 mA
Pin arrangement
SOJ
I/O0
I/O1
WE
RAS
A9
1
2
3
4
5
26
25
24
23
22
GND
I/O3
I/O2
CAS
OE
I/O0
I/O1
WE
RAS
A9
1
2
3
4
5
Pin designation
TSOP
26
25
24
23
22
GND
I/O3
I/O2
CAS
OE
Pin(s)
A0 to A9
RAS
I/O0 to I/O3
OE
CAS
WE
V
CC
GND
Description
Address inputs
Row address strobe
Input/output
Output enable
Column address strobe
Read/write control
Power (5.0
±
0.5V)
Ground
A0
A1
A2
A3
V
CC
9
10
11
12
13
18
17
16
15
14
A8
A7
A6
A5
A4
A0
A1
A2
A3
V
CC
9
10
11
12
13
18
17
16
15
14
A8
A7
A6
A5
A4
Selection guide
Symbol
Maximum RAS access time
Maximum column address access time
Maximum CAS access time
Maximum output enable (OE) access time
Minimum read or write cycle time
Minimum fast page mode cycle time
Maximum operating current
Maximum CMOS standby current
Shaded areas contain advance information.
4C14400-40
40
20
10
10
70
30
90
1.0
4C14400-50
50
25
13
13
90
35
80
1.0
4C14400-60
60
30
15
15
110
40
70
1.0
4C14400-70
70
35
18
18
130
45
60
1.0
Unit
ns
ns
ns
ns
ns
ns
mA
mA
t
RAC
t
CAA
t
CAC
t
OEA
t
RC
t
PC
I
CC1
I
CC5
ALLIANCE SEMICONDUCTOR