AS4C1M16E5
®
5V 1M×16 CMOS DRAM (EDO)
Features
• Organization: 1,048,576 words × 16 bits
• High speed
- 45/50/60 ns RAS access time
- 20/20/25 ns hyper page cycle time
- 10/12/15 ns CAS access time
• 1024 refresh cycles, 16 ms refresh interval
- RAS-only or CAS-before-RAS refresh Read-modify-write
• TTL-compatible, three-state DQ
• JEDEC standard package and pinout
- 400 mil, 42-pin SOJ
- 400 mil, 44/50-pin TSOP II
• Low power consumption
- Active: 740 mW max (AS4C1M16E5-60)
- Standby: 5.5 mW max, CMOS DQ
• 5V power supply (AS4C1M16E5)
• 3V power supply (AS4LC1M16E5)
• Industrial and commercial temperature available
• Extended data out
Pin arrangement
SOJ
Vcc
DQ1
DQ2
DQ3
DQ4
Vcc
DQ5
DQ6
DQ7
DQ8
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
V
SS
DQ16
DQ15
DQ14
DQ13
V
SS
DQ12
DQ11
DQ10
DQ9
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
V
SS
V
CC
DQ1
DQ2
DQ3
DQ4
V
CC
DQ5
DQ6
DQ7
DQ8
NC
Pin designation
TSOP II
1
2
3
4
5
6
7
8
9
10
11
50
49
48
47
46
45
44
43
42
41
40
V
SS
DQ16
DQ15
DQ14
DQ13
V
SS
DQ12
DQ11
DQ10
DQ9
NC
Pin(s)
A0 to A9
RAS
DQ1 to DQ16
OE
WE
UCAS
LCAS
V
CC
V
SS
Description
Address inputs
Row address strobe
Input/output
Output enable
Write enable
Column address strobe, upper byte
Column address strobe, lower byte
Power
Ground
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
V
CC
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
V
SS
Selection guide
Symbol
Maximum RAS access time
Maximum column address access time
Maximum CAS access time
Maximum output enable (OE) access time
Minimum read or write cycle time
Minimum hyper page mode cycle time
Maximum operating current
Maximum CMOS standby current
t
RAC
t
AA
t
CAC
t
OEA
t
RC
t
HPC
I
CC1
I
CC5
-45
45
23
10
12
75
20
155
1.0
-50
50
25
12
13
80
20
145
1.0
-60
60
30
15
15
100
25
135
1.0
Unit
ns
ns
ns
ns
ns
ns
mA
mA
4/11/01; v.1.0
Alliance Semiconductor
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