AS7C1024A
AS7C31024A
®
Write cycle (over the operating range)
Parameter
Write cycle time
Chip enable (CE1) to write end
Chip enable (CE2) to write end
Address setup to write end
Address setup time
Write pulse width
Write recovery time
Address hold from end of write
Data valid to write end
Data hold time
Write enable to output in high Z
Output active from write end
Symbol
t
WC
t
CW1
t
CW2
t
AW
t
AS
t
WP
t
WR
t
AH
t
DW
t
DH
t
WZ
t
OW
-10
Min Max
10
–
8
–
8
–
8
–
0
–
7
–
0
–
0
5
0
–
1
–
–
–
6
–
-12
Min Max
12
–
10
–
10
–
9
–
0
–
8
–
0
–
0
6
0
–
1
–
–
–
6
–
-15
Min Max
15
–
12
–
12
–
10
–
0
–
9
–
0
–
0
8
0
–
1
–
–
–
6
–
-20
Min Max
20
–
12
–
12
–
12
–
0
–
12
–
0
–
0
10
0
–
2
–
–
–
8
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
12
12
12
4, 5
4, 5
4, 5
Write waveform 1 (WE controlled)
t
WC
t
AW
Address
t
WP
WE
t
AS
D
IN
t
WZ
D
OUT
t
DW
Data valid
t
OW
t
DH
t
WR
t
AH
Write waveform 2 (CE1 and CE2 controlled)
t
AW
Address
t
AS
CE1
CE2
t
WP
WE
t
WZ
D
IN
D
OUT
t
DW
Data valid
t
DH
t
CW1
, t
CW2
t
WC
t
AH
t
WR
9/26/02; 0.9.9
Alliance Semiconductor
P. 5 of 9
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
