AS7C1025B
®
Functional description
The AS7C1025B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 131,072 x 8
bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 10/12/15/20 ns with output enable access times (t
OE
) of 5/6/7/8 ns are ideal for high-
performance applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory systems.
When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume I
SB
power. If the bus is static, then full
standby power is reached (I
SB1
). For example, the AS7C1026B is guaranteed not to exceed 55 mW under nominal full standby conditions.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O7 is written on
the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after
outputs have been disabled with
output enable (
OE
) or write enable
(WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chips drive I/O pins
with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output
drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The AS7C1025B is packaged in common
industry standard packages.
Absolute maximum ratings
Parameter
Voltage on V
CC
relative to GND
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Ambient temperature with V
CC
applied
DC current into outputs (low)
Symbol
V
t1
V
t2
P
D
T
stg
T
bias
I
OUT
Min
–0.50
–0.50
–
–65
–55
–
Max
+7.0
V
CC
+ 0.5
1.0
+150
+125
20
Unit
V
V
W
o
C
o
C
mA
NOTE: Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
H
L
L
L
WE
X
H
H
L
OE
X
H
L
X
Data
High Z
High Z
D
OUT
D
IN
Mode
Standby (I
SB
, I
SB1
)
Output disable (I
CC
)
Read (I
CC
)
Write (I
CC
)
Key: X = don’t care, L = low, H = high.
3/26/04, v. 1.3
Alliance Semiconductor
P. 2 of 9
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
