AS7C1025
AS7C31025
®
Data retention characteristics (over the operating range)
13
Parameter
V
CC
for data retention
Data retention current
Chip enable to data retention time
Operation recovery time
Input leakage current
Symbol
V
DR
I
CCDR
t
CDR
t
R
|
I
LI
|
Test conditions
V
CC
= 2.0V
CE
≥
V
CC
– 0.2V
V
IN
≥
V
CC
– 0.2V
or
V
IN
≤
0.2V
Min
2.0
–
0
t
RC
–
Max
–
500
–
–
1
Unit
V
µA
ns
ns
µA
Data retention waveform
Data retention mode
V
CC
V
CC
t
CDR
CE
V
IH
V
DR
V
IH
V
DR
≥
2.0V
V
CC
t
R
AC test conditions
–
–
–
–
5V output load: see Figure B or Figure C.
Input pulse level: GND to 3.0V. See Figure A.
Input rise and fall times: 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
Thevenin equivalent:
168W
D
OUT
+1.728V (5V and 3.3V)
+5V
480W
+3.0V
GND
90%
10%
2 ns
90%
10%
D
OUT
255W
C(14)
D
OUT
255W
+3.3V
320W
C(14)
Figure A: Input pulse
GND
Figure B: 5V Output load
GND
Figure C: 3.3V Output load
Notes
1
2
3
4
5
6
7
8
9
10
11
12
13
14
During V
CC
power-up, a pull-up resistor to V
CC
on CE is required to meet I
SB
specification.
This parameter is sampled, but not 100% tested.
For test conditions, see
AC Test Conditions,
Figures A, B, and C.
t
CLZ
and t
CHZ
are specified with CL = 5pF, as in Figure C. Transition is measured
±500mV
from steady-state voltage.
This parameter is guaranteed, but not 100% tested.
WE is High for read cycle.
CE and OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
All write cycle timings are referenced from the last valid address to the first transitioning address.
NA.
2V data retention applies to commercial temperature operating range only.
C=30pF, except all high Z and low Z parameters, where C=5pF.
3/23/01; v.1.0
Alliance Semiconductor
P. 6 of 9
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
