AS7C256A
®
AC test conditions
-
-
-
-
Output load: see Figure B
Input pulse level: GND to V
CC
See Figure A.
Input rise and fall times: 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
+5.0V
D
out
255
Ω
480
Ω
C
10
D
out
Thevenin equivalent
168
Ω
V
CC
GND
90%
10%
2 ns
90%
10%
+1.72V
Figure A: Input pulse
GND
Figure B: Output load
Notes
1
2
3
4
5
6
7
8
9
10
During V
CC
power-up, a pull-up resistor to V
CC
on CE is required to meet I
SB
specification.
For test conditions, see
AC Test Conditions,
Figures A, B.
These parameters are specified with CL = 5pF, as in Figures B. Transition is measured
±
500mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is High for read cycle.
CE and OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
All write cycle timings are referenced from the last valid address to the first transitioning address.
C=30pF, except on High Z and Low Z parameters, where C=5pF.
9/24/04; v.1.2
Alliance Semiconductor
P. 6 of 9
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
