March 2004
®
AS7C31024B
3.3V 128K X 8 CMOS SRAM
Features
• Industrial and commercial temperatures
• Organization: 131,072 words x 8 bits
• High speed
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
• Low power consumption: ACTIVE
- 252 mW / max @ 10 ns
• Easy memory expansion with CE1, CE2, OE inputs
• TTL/LVTTL-compatible, three-state I/O
• 32-pin JEDEC standard packages
-
-
-
-
300 mil SOJ
400 mil SOJ
8 × 20mm TSOP 1
8 x 13.4mm sTSOP 1
• Low power consumption: STANDBY
- 18 mW / max CMOS
• ESD protection
≥
2000 volts
• Latch-up current
≥
200 mA
• 6T 0.18u CMOS technology
Pin arrangement
Logic block diagram
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
V
CC
GND
Input buffer
A0
A1
A2
A3
A4
A5
A6
A7
A8
I/O7
Row decoder
512 x 256 x 8
Array
(1,048,576)
Sense amp
32-pin (8 x 20mm) TSOP I
32-pin (8 x 13.4mm) sTSOP1
I/O0
WE
OE
CE1
CE2
A11
A9
A8
A13
WE
CE2
A15
V
CC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
Selection guide
-10
-12
12
6
65
5
-15
15
7
60
5
AS7C31024B
Column decoder
Control
circuit
A9
A10
A11
A12
A13
A14
A15
A16
AS7C31024B
-20
20
8
55
5
Unit
ns
ns
mA
mA
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
10
5
70
5
3/24/04, v.1.2
Alliance Semiconductor
P. 1 of 9
Copyright © 2003 Alliance Semiconductor. All rights reserved.
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
