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AS7C31024B-10JCN 参数 Datasheet PDF下载

AS7C31024B-10JCN图片预览
型号: AS7C31024B-10JCN
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V 128K ×8 CMOS SRAM [3.3V 128K X 8 CMOS SRAM]
分类和应用: 静态存储器
文件页数/大小: 9 页 / 121 K
品牌: ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
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AS7C31024B
®
Read cycle (over the operating range)
3,9,12
-10
Parameter
Read cycle time
Address access time
Chip enable (CE1) access time
Chip enable (CE2) access time
Output enable (OE) access time
Output hold from address change
CE1 low to output in low Z
CE2 high to output in low Z
CE1 high to output in high Z
CE2 low to output in high Z
OE low to output in low Z
OE high to output in high Z
Power up time
Power down time
Symbol Min
t
RC
t
AA
t
ACE1
t
ACE2
t
OE
t
OH
t
CLZ1
t
CLZ2
t
CHZ1
t
CHZ2
t
OLZ
t
OHZ
t
PU
t
PD
10
3
3
3
0
0
Max
10
10
10
5
3
3
5
10
12
3
3
3
0
0
-12
Min
Max
12
12
12
6
3
3
6
12
15
3
3
3
0
0
-15
Min
Max
15
15
15
7
4
4
7
15
20
3
3
3
-20
Min
Max Unit
ns
20
20
20
8
Notes
3
3, 12
3, 12
5
4, 5, 12
4, 5, 12
4, 5, 12
4, 5, 12
4, 5
4, 5
4, 5, 12
4, 5, 12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
5
8
20
0
0
Key to switching waveforms
Rising input
Falling input
Undefined / don’t care
Read waveform 1 (address controlled)
3,6,7,9,12
t
RC
Address
D
OUT
t
AA
Data valid
t
OH
Read waveform 2 (CE1, CE2, and OE controlled)
3,6,8,9,12
CE1
CE2
OE
D
OUT
t
ACE1
,
tACE2
t
CLZ1
, t
CLZ2
t
PU
Data valid
t
PD
50%
50%
I
CC
I
SB
t
OE
t
OLZ
t
OHZ
t
CHZ1
, t
CHZ2
t
RC1
Supply
current
3/24/04, v.1.2
Alliance Semiconductor
P. 4 of 9