AS7C31024B
®
Write waveform 2 (CE1 and CE2 controlled)
10,11,12
t
AW
Address
t
AS
CE1
CE2
t
WP
WE
t
WZ
D
IN
D
OUT
t
DW
Data valid
t
DH
t
CW1
, t
CW2
t
WC
t
AH
t
WR
AC test conditions
–
–
–
–
Output load: see Figure B.
Input pulse level: GND to 3.0V. See Figure A.
Input rise and fall times: 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
Thevenin equivalent:
168Ω
D
OUT
+1.728V
+3.3V
320Ω
+3.0V
GND
90%
10%
2 ns
90%
10%
D
OUT
255Ω
C
13
Figure A: Input pulse
GND
Figure B: 3.3V Output load
Notes
1
2
3
4
5
6
7
8
9
10
11
12
13
14
During V
CC
power-up, a pull-up resistor to V
CC
on CE1 is required to meet I
SB
specification.
This parameter is sampled and not 100% tested.
For test conditions, see
AC Test Conditions,
Figures A, and B.
t
CLZ
and t
CHZ
are specified with CL = 5pF, as in Figure C. Transition is measured ±500 mV from steady-state voltage.
This parameter is guaranteed, but not 100% tested.
WE is high for read cycle.
CE1 and OE are low and CE2 is high for read cycle.
Address valid prior to or coincident with CE1 transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
N/A
All write cycle timings are referenced from the last valid address to the first transitioning address.
CE1 and CE2 have identical timing.
C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
N/A
3/24/04, v.1.2
Alliance Semiconductor
P. 6 of 9
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
