AS7C31026B
®
Functional description
The AS7C31026B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words
× 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for
high-performance applications.
When CE is high, the device enters standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data
on the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention,
external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chips drive I/O pins
with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output
drivers stay in high-impedance mode.
The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15.
All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3 V supply. The device is packaged in common industry
standard packages.
Absolute maximum ratings
Parameter
Symbol
Min
–0.50
–0.50
–
Max
Unit
V
Voltage on V relative to GND
V
V
+5.0
CC
t1
t2
D
Voltage on any pin relative to GND
Power dissipation
V
+0.50
V
CC
P
T
1.0
+150
+125
20
W
Storage temperature (plastic)
Ambient temperature with VCC applied
DC current into outputs (low)
–65
–55
–
°C
°C
mA
stg
bias
T
I
OUT
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
H
L
WE
X
OE
X
L
LB
X
L
UB
X
H
L
I/O0–I/O7
I/O8–I/O15
High Z
Mode
Standby (I ), I
High Z
)
SB SBI
H
D
High Z
Read I/O0–I/O7 (I
)
OUT
CC
L
H
L
H
L
High Z
D
D
Read I/O8–I/O15 (I
Read I/O0–I/O15 (I
OUT
OUT
CC)
L
H
L
L
D
)
CC
OUT
L
L
X
X
X
L
L
D
D
Write I/O0–I/O15 (I
)
CC
IN
IN
IN
L
L
L
H
L
D
High Z
Write I/O0–I/O7 (I
)
CC
L
L
H
High Z
D
Write I/O8–I/O15 (I
)
CC
IN
L
L
H
X
H
X
X
H
X
H
High Z
High Z
Output disable (I
)
CC
Key: H = high, L = low, X = don’t care.
3/26/04, v 1.3
Alliance Semiconductor
P. 2 of 10
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
