AS7C32098A
®
Write waveform 3 9
tWC
tAH
tWR
Address
CE
tAS
tCW
tAW
tBW
LB, UB
WE
tWP
tDW
Data valid
tDH
DataIN
tWZ
Data undefined
DataOUT
High Z
High Z
AC test conditions
- Output load: see Figure B.
- Input pulse level: GND to 3.0V. See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
+3.3V
320
Ω
+3.0V
DOUT
350
168Ω
90%
10%
90%
10%
Thevenin equivalent:
+1.728V
DOUT
Ω
C10
GND
2 ns
GND
Figure B: 3.3V Output load
Figure A: Input pulse
Notes
1
2
3
4
5
6
7
8
9
During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
For test conditions, see AC Test Conditions, Figures A and B.
t
CLZ and tCHZ are specified with CL = 5pF as in Figure B. Transition is measured ±500mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is High for read cycle.
CE and OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
All write cycle timings are referenced from the last valid address to the first transitioning address.
10 C=30pF, except on High Z and Low Z parameters, where C=5pF.
2/24/05,v. 1.0
Alliance Semiconductor
P. 7 of 10
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
