February 2005
Preliminary Information
AS7C32098A
®
3.3 V 128K × 16 CMOS SRAM
Features
• Industrial and commercial temperature
• Organization: 131,072 words × 16 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 4/5/6/7 ns output enable access time
- 28.8 mW /max CMOS
• Individual byte read/write controls
• Easy memory expansion with CE, OE inputs
• TTL- and CMOS-compatible, three-state I/O
• 44-pin JEDEC standard packages
• ESD protection
≥
2000 volts
• Latch-up current
≥
200 mA
- TSOP 2
• Low power consumption: ACTIVE
- 650 mW /max @ 10 ns
• Low power consumption: STANDBY
Logic block diagram
Pin arrangement for TSOP 2
A0
A1
A2
A3
A4
CE
I/O1
I/O2
I/O3
I/O4
V
CC
GND
I/O5
I/O6
I/O7
I/O8
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A16
A15
A14
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
GND
V
CC
I/O12
I/O11
I/O10
I/O9
NC
A13
A12
A11
A10
NC
A0
A1
A2
A3
A4
A6
A7
A8
A12
A13
I/O1–I/O8
I/O9–I/O16
WE
Row Decoder
V
CC
1024 × 128 × 16
Array
(2,097,152)
GND
I/O
buffer
Control circuit
Column decoder
A5
A9
A10
A11
A14
A15
A16
UB
OE
LB
CE
Selection guide
–10
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
Industrial
Commercial
10
4
180
170
8
–12
12
5
160
150
8
–15
15
6
140
130
8
–20
20
7
110
100
8
Unit
ns
ns
mA
mA
mA
2/24/05, v. 1.0
Alliance Semiconductor
P. 1 of 10
Copyright © Alliance Semiconductor. All rights reserved.