AS7C3256A
®
Write cycle (over the operating range)
11
-10
Parameter
Write cycle time
Chip enable to write end
Address setup to write end
Address setup time
Write pulse width
Write recovery time
Address hold from end of write
Data valid to write end
Data hold time
Write enable to output in high Z
Output active from write end
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
AH
t
DW
t
DH
t
WZ
t
OW
Min
10
8
8
0
7
0
0
5
0
–
3
Max
–
–
–
–
–
–
–
–
–
5
–
Min
12
8
8
0
8
0
0
6
0
–
3
-12
Max
–
–
–
–
–
–
–
–
–
6
–
Min
15
10
10
0
9
0
0
8
0
–
3
-15
Max
–
–
–
–
–
–
–
–
–
7
–
Min
20
12
12
0
12
0
0
10
0
–
3
-20
Max
–
–
–
–
–
–
–
–
–
8
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4, 5
4, 5
4, 5
Notes
Write waveform 1 (WE controlled)
10,11
t
AW
Address
WE
t
AS
D
in
t
WZ
D
out
t
WP
t
DW
Data valid
t
OW
t
WR
t
DH
t
WC
t
AH
Write waveform 2 (CE controlled)
10,11
t
AW
Address
t
AS
CE
t
WP
WE
t
WZ
D
in
D
out
t
DW
Data valid
t
DH
t
CW
t
WR
t
WC
t
AH
4/23/04; v.2.0
Alliance Semiconductor
P. 5 of 9
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
