December 2004
®
AS7C331MPFS18A
3.3V 1M x 18 pipelined burst synchronous SRAM
Features
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Organization: 1,048,576 x18 bits
Fast clock speeds to 166MHz
Fast clock to data access: 3.4/3.8 ns
Fast OE access time: 3.4/3.8 ns
Fully synchronous register-to-register operation
Single-cycle deselect
Asynchronous output enable control
Available 100-pin TQFP package
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Individual byte write and global write
Multiple chip enables for easy expansion
3.3 V core power supply
2.5 V or 3.3V I/O operation with separate V
DDQ
Linear or interleaved burst control
Common data inputs and data outputs
Snooze mode for reduced power-standby
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[19:0]
CLK
CS
CLR
Burst logic
Q
20
CS
Address
D
20
18 20
1M x 18
Memory
array
18
18
register
CLK
GWE
BW
b
BWE
BW
a
CE0
CE1
CE2
D
DQb
Q
CLK
D
DQa
Q
Byte Write
registers
Byte Write
registers
CLK
D
2
OE
CE
CLK
D
ZZ
Enable
register
Q
Output
registers
CLK
Input
registers
CLK
Power
down
Enable
Q
delay
register
CLK
OE
18
DQ[a,b]
Selection guide
-166
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
6
166
3.4
290
90
60
-133
7.5
133
3.8
270
80
60
Units
ns
MHz
ns
mA
mA
mA
12/23/04, v 2.6
Alliance Semiconductor
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ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
