April 2005
®
AS7C33512NTD32A
AS7C33512NTD36A
3.3V 512K × 32/36 Pipelined SRAM with NTD
TM
Features
•
•
•
•
•
•
•
•
•
Organization: 524,288 words × 32 or 36 bits
NTD
™
architecture for efficient bus operation
Fast clock speeds to 166 MHz
Fast clock to data access: 3.4/3.8 ns
Fast OE access time: 3.4/3.8 ns
Fully synchronous operation
Asynchronous output enable control
Available in 100-pin TQFP packages
Individual byte write and global write
•
•
•
•
•
•
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Clock enable for operation hold
Multiple chip enables for easy expansion
3.3V core power supply
2.5V or 3.3V I/O operation with separate V
DDQ
Self-timed write cycles
Interleaved or linear burst modes
Snooze mode for standby operation
Logic block diagram
A[18:0]
19
D
Address
register
Burst logic
Q
19
CLK
CE0
CE1
CE2
R/W
BWa
BWb
BWc
BWd
ADV / LD
LBO
ZZ
D
Q
19
Write delay
addr. registers
CLK
Control
logic
CLK
Write Buffer
CLK
512K x 32/36
SRAM
Array
DQ[a,b,c,d]
32/36
D
Data
Q
Input
Register
CLK
32/36
32/36
32/36
32/36
CLK
CEN
CLK
OE
Output
Register
32/36
OE
DQ[a,b,c,d]
Selection guide
-166
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
6
166
3.4
300
90
60
-133
7.5
133
3.8
275
80
60
Units
ns
MHz
ns
mA
mA
mA
4/21/05, v 2.8
Alliance Semiconductor
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