November 2004
®
AS7C33512PFS18A
3.3V 512K
×
18 pipeline burst synchronous SRAM
Features
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•
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•
•
•
•
•
•
Organization: 524,288 words × 18 bits
Fast clock speeds to 166 MHz
Fast clock to data access: 3.5/4.0 ns
Fast OE access time: 3.5/4.0 ns
Fully synchronous register-to-register operation
Single-cycle deselect
Asynchronous output enable control
Available in 100-pin TQFP package
Individual byte write and global write
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Multiple chip enables for easy expansion
3.3V core power supply
2.5V or 3.3V I/O operation with separate V
DDQ
30 mW typical standby power in power down mode
Linear or interleaved burst control
Snooze mode for reduced power-standby
Common data inputs and data outputs
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[18:0]
CLK
CS
CLR
Burst logic
Q
19
CS
Address
register
CLK
D
19
17 19
512K × 18
Memory
array
18
18
GWE
BW
b
BWE
BW
a
CE0
CE1
CE2
D
DQb
Q
CLK
D
DQa
Q
Byte Write
registers
Byte Write
registers
CLK
D
2
OE
CE
CLK
ZZ
Enable
register
Q
Output
registers
CLK
Input
registers
CLK
Power
down
D
Enable
Q
delay
register
CLK
OE
18
DQ[a,b]
Selection guide
–166
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
6
166
3.5
475
130
30
–133
7.5
133
4
425
100
30
Units
ns
MHz
ns
mA
mA
mA
11/30/04;
v.2.2
Alliance Semiconductor
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