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AS7C34098A-15JCN 参数 Datasheet PDF下载

AS7C34098A-15JCN图片预览
型号: AS7C34098A-15JCN
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3 V 256的K× 16的CMOS SRAM [3.3 V 256 K x 16 CMOS SRAM]
分类和应用: 静态存储器
文件页数/大小: 10 页 / 152 K
品牌: ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
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AS7C34098A
®
Read cycle (over the operating range)
3,9
–10
Parameter
Read cycle time
Address access time
Chip enable (CE) access time
Output enable (OE) access time
Output hold from address change
CE Low to output in low Z
CE High to output in high Z
OE Low to output in low Z
OE High to output in high Z
LB, UB access time
LB, UB Low to output in low Z
LB, UB High to output in high Z
Power up time
Power down time
Symbol
t
RC
t
AA
t
ACE
t
OE
t
OH
t
CLZ
t
CHZ
t
OLZ
t
OHZ
t
BA
t
BLZ
t
BHZ
t
PU
t
PD
Min
10
3
3
0
0
0
Max
10
10
4
5
5
5
5
10
12
3
3
0
0
0
–12
Min
Max
12
12
5
6
6
6
6
12
15
3
3
0
0
0
–15
Min
Max
15
15
6
7
7
7
7
15
20
3
3
0
0
0
–20
Min
Max
20
20
7
9
9
8
9
20
Unit Notes
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
5
5
4, 5
4, 5
4, 5
4, 5
Key to switching waveforms
Rising input
Falling input
Undefined/don’t care
Read waveform 1 (address controlled)
6,7,9
t
RC
Address
t
OH
Data
OUT
Previous data valid
t
AA
Data valid
t
OH
8/17/04,v. 2.1
Alliance Semiconductor
P. 4 of 10