AS7C34098A
®
Functional description
The AS7C34098A is a high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as
262,144 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are
desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 10/12/15/20 ns with output enable access times (t
OE
) of 4/5/6/7 ns are
ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank
memory systems.
When CE is high the device enters standby mode. The device is guaranteed not to exceed 28.8mW power consumption in
CMOS standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input
pins I/O1–I/O16 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external
devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or
write enable is active, output drivers stay in high-impedance mode.
The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16.
All chip inputs and outputs are TTL- and CMOS-compatible, and operation is for 3.3V (AS7C34098A) supply. The device is
available in the JEDEC standard 400-mL, 44-pin SOJ, TSOP 2.
Absolute maximum ratings
Parameter
Voltage on V
CC
relative to GND
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Ambient temperature with V
CC
applied
DC current into outputs (low)
Symbol
V
t1
V
t2
P
D
T
stg
T
bias
I
OUT
Min
–0.50
–0.50
–
–65
–55
–
Max
+5.0
V
CC
+0.50
1.5
+150
+125
±20
Unit
V
V
W
°C
°C
mA
Note: Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
H
L
L
WE
X
H
X
OE
X
H
X
LB
X
X
H
L
L
H
L
H
L
L
L
L
X
H
L
Key: X = Don’t care, L = Low, H = High.
UB
X
X
High Z
H
H
L
L
H
L
L
D
OUT
High Z
D
OUT
D
IN
High Z
D
IN
High Z
D
OUT
D
OUT
High Z
D
IN
D
IN
Write (I
CC
)
Read (I
CC
)
High Z
Output disable (I
CC
)
I/O1–I/O8
High Z
I/O9–I/O16
High Z
Mode
Standby (I
SB
, I
SB1
)
8/17/04,v. 2.1
Alliance Semiconductor
P. 2 of 10
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
