AS7C4098
AS7C34098
®
Write waveform 3
10,11
t
WC
t
AH
t
WR
Address
t
AS
CE
t
AW
t
BW
LB, UB
WE
Data
IN
Data
OUT
High Z
t
WZ
Data undefined
t
WP
t
DW
Data valid
t
DH
High Z
t
CW
AC test conditions
-
-
-
-
Output load: see Figure B or Figure C.
Input pulse level: GND to 3.0V. See Figure A.
Input rise and fall times: 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
+3.0V
GND
90%
10%
2 ns
Figure A: Input pulse
90%
10%
Thevenin equivalent: D
OUT
+5V
D
OUT
255Ω
480Ω
C
13
168Ω
+1.728V (5V and 3.3V)
+3.3V
320Ω
C
13
D
OUT
350Ω
GND
Figure B: 5V Output load
GND
Figure C: 3.3V Output load
Notes
1
2
3
4
5
6
7
8
9
10
11
12
13
During V
CC
power-up, a pull-up resistor to V
CC
on CE is required to meet I
SB
specification.
This parameter is sampled, but not 100% tested.
For test conditions, see
AC Test Conditions,
Figures A, B, C.
t
CLZ
and t
CHZ
are specified with C
L
= 5pF as in Figure C. Transition is measured ±500mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is High for read cycle.
CE and OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
All write cycle timings are referenced from the last valid address to the first transitioning address.
Not applicable.
C = 30pF, except on High Z and Low Z parameters, where C = 5pF.
1/13/05;
v.1.9
Alliance Semiconductor
P. 7 of 10
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
