AS7C4096A
®
Write waveform 2 (CE controlled)
9
t
WC
t
AW
Address
t
AS
CE
WE
D
IN
t
WP
t
DW
Data valid
t
DH
t
CW
t
WR
t
AH
AC test conditions
-
-
-
-
Output load: see Figure B.
Input pulse level: GND to V
CC
- 0.5V. See Figures A and B.
Input rise and fall times: 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
D
OUT
255Ω
+5.0V
480Ω
C
10
Thevenin equivalent:
168Ω
D
OUT
+1.728V
V
CC
- 0.5V
GND
90%
10%
90%
10%
2 ns
Figure A: Input pulse
GND
Figure B: 5.0V Output load
Notes
1
2
3
4
5
6
7
8
9
10
During V
CC
power-up, a pull-up resistor to V
CC
on CE is required to meet I
SB
specification.
For test conditions, see
AC Test Conditions.
t
CLZ
and t
CHZ
are specified with C
L
= 5pF as in Figure B. Transition is measured ±500 mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is HIGH for read cycle.
CE and OE are LOW for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
All write cycle timings are referenced from the last valid address to the first transitioning address.
C = 30pF, except at high Z and low Z parameters, where C = 5pF.
5/27/05, v. 1.1
Alliance Semiconductor
P. 6 of 10
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
