AS7C4096A
®
Functional description
The AS7C4096A is a high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as
524,288 words × 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are
desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 10/12/15/20 ns with output enable access times (t
OE
) of 5/6 ns are ideal
for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory
systems.
When CE is high the device enters standby mode. The device is guaranteed not to exceed 55mW power consumption in CMOS
standby mode.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1–I/O8 is written
on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins
only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write
enable is active, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5.0V supply voltage. This device is available as
per industry standard 400-mil 36-pin SOJ and 44-pin TSOP 2 packages.
Absolute maximum ratings
Parameter
Voltage on V
CC
relative to GND
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Temperature with V
CC
applied
DC current into output (low)
Symbol
V
t1
V
t2
P
D
T
stg
T
bias
I
OUT
Min
–0.5
–0.5
–
–65
–55
–
Max
+7.0
V
CC
+0.5
1.0
+150
+125
20
Unit
V
V
W
°C
°C
mA
NOTE: Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
WE
OE
Data
Mode
H
L
L
L
X
H
H
L
X
H
L
X
High Z
High Z
D
OUT
D
IN
Standby (I
SB
, I
SB1
)
Output disable (I
CC
)
Read (I
CC
)
Write (I
CC
)
5/27/05, v. 1.1
Alliance Semiconductor
P. 2 of 10
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
