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ASM3P623S00EG-16-TR 参数 Datasheet PDF下载

ASM3P623S00EG-16-TR图片预览
型号: ASM3P623S00EG-16-TR
PDF下载: 下载PDF文件 查看货源
内容描述: 零周跳峰值EMI降低IC [Zero Cycle Slip Peak EMI reduction IC]
分类和应用:
文件页数/大小: 16 页 / 297 K
品牌: ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
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July 2005
rev 1.0
ASM3P623S00A/B/C/D/E/F
Zero Cycle Slip Peak EMI reduction IC
General Features
Input frequency range: 20MHz - 50MHz.
Zero input - output propagation delay.
Low-skew outputs.
Output-output skew less than 250pS.
Device-device skew less than 700pS.
Less than 200pS cycle-to-cycle jitter is compatible
with Pentium
®
based systems.
Available in 16pin, 150mil SOIC, 4.4mm TSSOP
(ASM3P623S00D/E/F), and in 8pin, 150 mil SOIC,
4.4mm TSSOP Packages (ASM3P623S00A/B/C).
3.3V operation
Advanced 0.35µ CMOS technology.
The First True Drop-in Solution.
All parts have on-chip PLLs that lock to an input clock on
the CLKIN pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad, internal to the device.
Multiple ASM3P623S00D/E/F devices can accept the same
input clock and distribute it. In this case, the skew between
the outputs of the two devices is guaranteed to be less than
700pS.
All outputs have less than 200pS of cycle-to-cycle jitter.
The input and output propagation delay is guaranteed to be
less than 250pS, and the output-to-output skew is
guaranteed to be less than 250pS.
Please refer
Differential Cycle Slips and Spread Spectrum
Control Table” for deviations and differential Cycle Slips
for ASM3P623S00A/B/C and the ASM3P623S00D/E/F
devices
Functional Description
ASM3P623S00D/E/F is a versatile, 3.3V zero-delay buffer
designed to distribute high-speed clocks. It accepts one
reference input and drives out eight low-skew clocks. It is
available in a 16pin package. The ASM3P623S00A/B/C is
the eight-pin version of the ASM3P623S00. It accepts one
reference input and drives out one low-skew clock.
The ASM3P623S00A/B/C and the ASM3P623S00D/E/F
are available in two different configurations, as shown in
the ordering information table.
Block Diagram
V
DD
SSON
SS%
Modulation
Reference
Divider
Feedback
Divider
PLL
CLKIN
Phase
Detector
Loop
Filter
VCO
Feedforward
Divider
CLKOUT
V
SS
Alliance Semiconductor
2575 Augustine Drive
Santa Clara, CA
Tel: 408.855.4900
Fax: 408.855.4999
www.alsc.com
Notice: The information in this document is subject to change without notice.