ASM811TEUS-T 参数 Datasheet PDF下载

October 2003

rev 1.0

Symbol

Parameter

MR Glitch Immunity

t

MD

V

IH

V

IL

V

IH

V

IL

MR Pullup Resistance

V

CC

= V

TH

min., I

SINK

= 1.2mA,

ASM811R/S/T

V

OL

Low RESET Output Voltage

(ASM811)

V

CC

= V

TH

min., I

SINK

= 3.2mA,

ASM811L/M/J

V

CC

> 1.1V, I

SINK

= 50µA

V

CC

> V

TH

max., I

SOURCE

= 500µA,

ASM811R/S/T

V

CC

> V

TH

max., I

SOURCE

= 800µA,

ASM811L/M/J

V

CC

= V

TH

max., I

SINK

= 1.2mA,

ASM812R/S/T

V

CC

= V

TH

max., I

SINK

= 3.2mA,

ASM812L/M/J

V

OH

T

RST

T

MRST

High RESET Output Voltage

(ASM812)

Active Reset Timeout Period

Manual Active Reset Time-

out Period

1.8V < V

CC

< V

TH

min., I

SOURCE

= 150µA

V

CC

> V

TH

MR returns HIGH

0.8V

CC

140

0.8V

CC

MR Input Threshold

MR to RESET Propogation

Delay

MR Input Threshold

ASM811, ASM812

Conditions

Note 3

Note 2

V

CC

> V

TH

(MAX),

ASM811/812L/M/J

V

CC

> V

TH

(MAX),

ASM811/812R/S/T

2.3

V

0.8

0.77V

CC

0.25V

CC

10

20

30

0.3

kΩ

Min

Typ

100

0.5

Max

Unit

ns

µs

V

0.4

V

0.3

V

OH

High RESET Output Voltage

(ASM811)

V

V

CC

- 1.5

0.3

V

0.4

V

240

180

msec

msec

V

OL

Low RESET Output Voltage

(ASM812)

Notes:

1. Production testing done at TA = 25°C. Over-temperature specifications guaranteed by design only using six sigma design limits.

2. RESET output is active LOW for the ASM811 and RESET output is active HIGH for the ASM812.

3. Glitches of 100ns or less typically will not generate a reset pulse.

4 Pin µP Voltage Supervisor with Manual Reset

Notice: The information in this document is subject to change without notice

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